Run-time correction of defect locations during defect review

Patent metadata

Field	Value
Publication number	US-10354405-B2
Application number	US-78153210-A
Country	US
Kind code	B2
Filing date	May 17, 2010
Priority date	May 17, 2010
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

One embodiment relates to a method for run-time correction of defect locations on a substrate during defect review. The substrate is loaded into a stage of a review apparatus, and coordinates for the defect locations on the substrate is received. The defect locations are grouped, and at least one local reference site in proximity to each group of defect locations is determined. The local reference site(s) is (are) used to determine a positional offset for the defect locations in each group. Another embodiment relates to an apparatus for reviewing defect locations on a substrate which provides for run-time correction of the defect locations. Other embodiments and features are also disclosed.

First claim

What is claimed is:

1. A method for run-time correction of defect locations on a substrate during defect review, the method comprising:
loading the substrate into a stage of a review apparatus, the review apparatus comprising a source for generating an electron beam, deflectors configured to scan the electron beam over a field of view, electron lenses for focusing the electron beam onto a surface of a substrate being reviewed, a detector for detecting electrons from the substrate, and electronic control and image analysis circuitry;
receiving coordinates for the defect locations on the substrate as detected by an inspection system;
sorting and grouping the defect locations by the electronic control and image analysis circuitry so as to provide a sequence of groups of defect locations and a sequence of the defect locations within each group;
determining at least one local reference site in proximity to each group of defect locations by the electronic control and image analysis circuitry; and
using the local reference site(s) to determine, by the electronic control and image analysis circuitry, a positional offset for the defect locations in each group by obtaining run-time image data of the local reference site by the review apparatus and calculating the positional offset by comparing the run-time image data against data of the reference site(s) obtained by the inspection system;
selecting a first group in the sequence of groups;
imaging the defect locations within the first group in an order specified by the sequence of defect locations within the first group, wherein said imaging obtains run-time image data for each defect location in each group by imaging a field of view located at a corrected position that is the coordinates of the defect location from the inspection system plus the positional offset for the defect locations in the group to which the defect belongs; and
repeating selection of a next group in the sequence of groups and imaging the defect location within the next group in an order specified by the sequence of defect location within the next group, until there is no further groups to select in the sequence of groups.

2. The method of claim 1 , wherein the method is performed by an inspection and review system based on scanning electron microscope apparatus.

3. The method of claim 1 , wherein the substrate comprises a patterned semiconductor wafer.

4. The method of claim 1 , wherein the run-time image data is obtained from a field of view which is less than a micron in diameter.

5. The method of claim 1 , wherein the method corrects for positioning errors with submicron accuracy.

6. An apparatus for reviewing defect locations on a substrate which provides for run-time correction of the defect locations, the apparatus comprising:
a source configured to generate an electron beam;
deflectors configured to scan the electron beam over a field of view;
electron lenses configured to focus the electron beam onto a surface of a substrate being reviewed;
a detector configured to detect electrons from the substrate; and
electronic control and image analysis circuitry configured to retrieve a list of defect locations on the substrate, sort and group the defect locations so as to provide a sequence of groups of defect locations and a sequence of the defect locations within each group, determine one or more local reference site in proximity to each defect location, and use the local reference site(s) to determine a positional offset for the defect location by obtaining run-time image data of the local reference site by the review apparatus and calculating the positional offset by comparing the run-time image data against data of the reference site(s) obtained by the inspection system,
wherein the electronic control and image analysis circuitry performs steps including selecting a first group in the sequence of groups, imaging the defect locations within the first group in an order specified by the sequence of defect locations within the first group, wherein said imaging obtains run-time image data for each defect location in each group by imaging a field of view located at a corrected position that is the coordinates of the defect location from the inspection system plus the positional offset for the defect locations in the group to which the defect belongs, and repeating selection of a next group in the sequence of groups and imaging the defect location within the next group in an order specified by the sequence of defect location within the next group, until there is no further groups to select in the sequence of groups.

7. The apparatus of claim 6 , wherein the substrate comprises a patterned semiconductor wafer.

8. The apparatus of claim 6 , wherein the run-time image data is obtained from a field of view which is less than a micron in diameter.

Assignees

• Lee Jeong Ho
• Kla Tencor Corp

Inventors

• Lee Jeong Ho

Classifications

• G06T7/73 Primary

  using feature-based methods · CPC title

• G06T2207/10061

  from scanning electron microscope · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06T2207/30204

  Marker · CPC title

• G06F18/00

  Pattern recognition · CPC title