Power-driven synthesis under latency constraints

Patent metadata

Field	Value
Publication number	US-10354183-B2
Application number	US-201414537857-A
Country	US
Kind code	B2
Filing date	Nov 10, 2014
Priority date	Nov 10, 2014
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.

First claim

What is claimed is:

1. A method for optimizing placement in a multi-core neurosynaptic network under latency constraints, the method comprising:
modeling power consumption of a neurosynaptic network as wire length within a model, the neurosynaptic network comprising a plurality of neurosynaptic cores and each of the plurality of neurosynaptic cores being modeled as a node in a placement graph within the model, the graph having a plurality of edges;
assigning a weight to each of the plurality of edges within the model based on a spike frequency;
determining a first physical arrangement of the neurosynaptic cores, the first physical arrangement corresponding to a length of each of the plurality of edges within the model;
comparing a maximum length constraint to the length of each of the plurality of edges in the model;
increasing the weight of at least one of the plurality of edges in the model having a length greater than the maximum length constraint; and
determining a second physical arrangement of the neurosynaptic cores, the second physical arrangement corresponding to a mapping of the neurosynaptic cores on a chip and minimizing weighted wirelength in the model relative to the first arrangement, thereby finding a physical location of the neurosynaptic cores on the chip that minimizes overall power consumption of the chip.

2. The method of claim 1 , wherein the determining the arrangement of the neurosynaptic cores comprises:
observing at least one placement legality constraint.

3. The method of claim 2 , wherein the at least one placement legality constraint comprises avoiding overlapping of the neurosynaptic cores.

4. The method of claim 1 , wherein the determining the arrangement of the neurosynaptic cores comprises:
minimizing the wire length.

5. The method of claim 4 , wherein the minimizing the wire length comprises applying a VLSI placement algorithm.

6. The method of claim 5 , wherein the VLSI placement algorithm comprises partitioning-based placement.

7. The method of claim 1 , wherein the neurosynaptic network further comprises a plurality of neuron-axon connections, and wherein each of the plurality of edges correspond to one of the neuron-axon connections.

8. The method of claim 1 , wherein each of the plurality of neuron-axon connections has a source core and a destination core, and wherein the plurality of edges does not include edges corresponding to those neuron-axon connections whose source core and destination core are the same.

9. The method of claim 1 , further comprising:
configuring the chip to execute the neurosynaptic cores according to the second arrangement.

10. A computer program product for optimizing placement in a multi-core neurosynaptic network under latency constraints, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
modeling power consumption of a neurosynaptic network as wire length within a model, the neurosynaptic network comprising a plurality of neurosynaptic cores and each of the plurality of neurosynaptic cores being modeled as a node in a placement graph within the model, the graph having a plurality of edges;
assigning a weight to each of the plurality of edges within the model based on a spike frequency;
determining a first physical arrangement of the neurosynaptic cores, the first physical arrangement corresponding to a length of each of the plurality of edges within the model;
comparing a maximum length constraint to the length of each of the plurality of edges in the model;
increasing the weight of at least one of the plurality of edges in the model having a length greater than the maximum length constraint; and
determining a second physical arrangement of the neurosynaptic cores, the second physical arrangement corresponding to a mapping of the neurosynaptic cores on a chip and minimizing weighted wirelength in the model relative to the first arrangement, thereby finding a physical location of the neurosynaptic cores on the chip that minimizes overall power consumption of the chip.

11. The computer program product of claim 10 , wherein the determining the arrangement of the neurosynaptic cores comprises:
observing at least one placement legality constraint.

12. The computer program product of claim 11 , wherein the at least one placement legality constraint comprises avoiding overlapping of the neurosynaptic cores.

13. The computer program product of claim 10 , wherein the determining the arrangement of the neurosynaptic cores comprises:
minimizing the wire length.

14. The computer program product of claim 13 , wherein the minimizing the wire length comprises applying a VLSI placement algorithm.

15. The computer program product of claim 14 , wherein the VLSI placement algorithm comprises partitioning-based placement.

16. The computer program product of claim 10 , wherein the neurosynaptic network further comprises a plurality of neuron-axon connections, and wherein each of the plurality of edges correspond to one of the neuron-axon connections.

17. The computer program product of claim 10 , wherein each of the plurality of neuron-axon connections has a source core and a destination core, and wherein the plurality of edges does not include edges corresponding to those neuron-axon connections whose source core and destination core are the same.

18. The computer program product of claim 10 , the method further comprising:
configuring the chip to execute the neurosynaptic cores according to the second arrangement.

Assignees

• IBM

Inventors

• Alpert Charles J
• Datta Pallab
• Flickner Myron D
• Li Zhuo
• Modha Dharmendra S
• Nam Gi-Joon

Classifications

• Y02D10/152

  Cross-Sectional Technologies · mapped topic

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title