Method and apparatus for fast context cloning in a data processing system

Patent metadata

Field	Value
Publication number	US-10353826-B2
Application number	US-201715649976-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Jul 14, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.

First claim

The invention claimed is:

1. A data processing system comprising:
a memory system;
a processing element;
a first address translator configured to map virtual addresses to system addresses;
a second address translator configured to maps system address to physical addresses; and
a task management unit;
where a first program task uses a first virtual memory space that is mapped to a first range of system address using a first range table,
where a context of the first program task includes an address of the first range table and is cloned by creating a second range table indicative of a mapping from a second virtual memory space to a second range of system addresses, where the second range of system addresses is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated, and
where the cloned context includes an address of the second range table.

2. The data processing system of claim 1 , where divisions of system addresses in the first and second range tables that are mapped to the same physical addresses are indicated by setting copy-on-write bits in the first and second range tables.

3. The data processing system of claim 2 where subsequent to beginning execution of a second program task in the cloned context:
when a write occurs to an address in the first virtual memory space that is mapped to a first division of the system address space and for which an associated copy-on-write bit is set:
allocating space in a physical memory device of the memory system;
copying data associated with the first division to the allocated space;
updating the system address to physical address mapping of the second address translator to include a new system address range having a second division that maps to the allocated space;
updating the second range table to translate the address in the first virtual memory space to the new system address range; and
clearing the copy-on-write bits in the first and second range tables.

4. The data processing system of claim 2 , where a division of the system address space comprises a cache line.

5. The data processing system of claim 1 , where the memory system comprises a coherent memory system, where the processing element comprises a first processing element, and where the data processing system further comprises:
one or more second processing elements that share the coherent memory system with the first processing element.

6. The data processing system of claim 1 , where the context of the first program task is cloned in response to a signal from the processing unit, a scheduler in the task manager or an external signal driven by a system scheduler mechanism.

7. A non-transient computer readable medium having instructions of a hardware description language or netlist representative of the data processing system of claim 1 .

8. The data processing system of claim 1 , where a context comprises:
virtual context format data including a register buffer address (RBA) of saved register data and a range table address (RTA) of a range table;
a register format that identifies how register values stored in memory are mapped to registers of the processing element; and
a subset of context data sufficient to begin or continue a program task.

9. The data processing system of claim 8 , where cloning of the context of the first program task is performed in hardware by selecting a virtual context format, mapping register data to registers of the processing element, and selecting an appropriate range table.

10. The data processing system of claim 1 , where:
the system addresses are located in a system address space having a plurality of address ranges, each address range of the plurality of address ranges comprising one or more divisions, and
the memory system comprises one or more physical memory devices and is addressable by the system addresses using the second address translator.

11. A method comprising:
executing a first program task in a processing element of a data processing system, where the first program tasks uses a first virtual memory space that is mapped, by a first address translator, to a first range of system addresses using a first range table, where the first range of system addresses is mapped, by a second address translator, to physical addresses in a memory system of the data processing system and where a context of the first program task includes an address of the first table;
cloning the context of the first program task, to produce a context for a second program task, by creating a second range table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range of system addresses is mapped, by the second address translator, to the same physical addresses in the memory system as the first range until a write to a mapped physical address occurs and where the context of the second program task includes an address of the second range table; and
when a write to a mapped physical address occurs:
allocating memory in the memory system; and
updating the mapping of the second range in the second range table.

12. The method of claim 11 where the system addresses are located in a system address space having a plurality of address ranges, each address range of the plurality of address ranges comprising one or more divisions, and where divisions of system addresses in the first and second range tables that are mapped to the same physical addresses in the memory system are indicated by setting copy-on-write bits in the first and second range tables.

13. The method of claim 11 , where a context comprises:
virtual context format data including a register buffer address (RBA) of saved register data and a range table address (RTA) of a range table;
a register format that identifies how register values stored in memory are mapped to registers of the processing element; and
a subset of context data sufficient to begin or continue a program task.

14. The method of claim 13 , where cloning of the context of the first program task is performed in hardware by selecting a virtual context format, mapping register data to registers of the processing element, and selecting an appropriate range table.

15. The method of claim 12 , further comprising, during execution of the second program task in the cloned context:
when a write occurs to an address in the first virtual memory space that is mapped to a first division of the system address space and for which an associated copy-on-write bit is set:
allocating space in a physical memory device of the memory system;
copying data associated with the first division to the allocated space;
updating the system address to physical address mapping of the second address translator to include a new system address range having a second division that maps to the allocated space;
updating the second range table to translate the address in the first virtual memory space to the new system address range; and
clearing the copy-on-write bits in the first and second range tables.

16. The data processing system of claim 12 , where a division of the system address space comprises a cache line.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Beard Jonathan Curtis
• Rusitoru Roxana
• Dunham Curtis Glenn

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F12/1063 Primary

  the data cache being concurrently virtually addressed · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title