Supply margining method and apparatus

Patent metadata

Field	Value
Publication number	US-10353449-B2
Application number	US-201514863393-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Mar 31, 2008
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

First claim

What is claimed is:

1. An apparatus comprising:
circuitry of a first voltage regulator (VR) to provide a first power supply to a first power domain;
circuitry of a second VR to provide a second power supply to a second power domain separate from the first power domain;
first one or more nodes to receive a voltage command request from a processor, wherein the voltage command request is to set a power supply delivered by at least one of the first and second VRs;
second one or more nodes to provide telemetry information, associated with at least one of the first and second VRs, to the processor; and
temperature monitor circuitry for at least one of the first and second VRs, wherein the temperature monitor circuitry is to monitor temperature of the at least one of the first and second VRs and alert the processor about the monitored temperature;
wherein the first and second power domains are part of the processor;
wherein the first VR circuitry is to provide an initial first power supply to the first power domain,
wherein the initial first power supply has a voltage level lower than a target operational supply level,
wherein the telemetry information includes voltage and current information, and the monitored temperature, and
wherein the circuitry of the first VR is to be coupled to an inductor.

2. The apparatus of claim 1 comprises logic shared between the first and second VR circuitry.

3. The apparatus of claim 1 , wherein the first power domain is at least a portion of a processor.

4. The apparatus of claim 3 , wherein the first VR is an integrated voltage regulator with a semiconductor die, switching elements, and magnetic components integrated into a common package.

5. The apparatus of claim 1 , wherein the circuitry of at least one of the first and second VRs include: an inductor; a capacitor; and switchable transistors.

6. The apparatus of claim 1 , wherein each circuitry of the first and second VRs is to be coupled to off-die switchable transistors, wherein the switchable transistors are coupled to an off-die inductor, and wherein the off-die inductor is coupled to an off-die capacitor.

7. The apparatus of claim 1 , wherein the first VR is operable with first voltage guardband values associated with upper and lower limits associated with the voltage command request.

8. The apparatus of claim 1 , wherein the processor is operable to determine second voltage guardband values associated with upper and lower limits of the allowable voltage command values.

9. The apparatus of claim 8 , wherein the second voltage guardband values are determined based on a difference between the received supply voltage and a requested supply voltage.

10. The apparatus of claim 9 , wherein the first voltage guardband values are higher than the second voltage guardband values.

11. The apparatus of claim 1 , wherein the first VR is an integrated voltage regulator with a semiconductor die, switching elements, and magnetic components integrated into a common package.

12. The apparatus of claim 1 , wherein the first or second VR when operated is switched in excess of 10 MHz.

13. The apparatus of claim 1 , wherein the first or second VR and processor are part of a common package.

14. The apparatus of claim 1 , wherein the telemetry information has responsiveness of at least 200 ns.

15. An apparatus comprising:
a portion of a first voltage regulator (VR) to provide a first power supply to a first power domain;
a portion of a second VR to provide a second power supply to a second power domain separate from the first power domain;
an interface which is to:
receive a voltage command request from a processor, wherein the voltage command request is to set a power supply delivered by at least one of the portions of the first and second VRs;
provide telemetry information, associated with at least one of the portions of the first and second VRs, to the processor; and

one or more circuits to monitor temperature of at least one of the portions of the first and second VRs, wherein the one or more circuits is to alert the processor about the monitored temperature;
wherein the first and second power domains are part of the processor;
wherein the first VR circuitry is to provide an initial first power supply to the first power domain, and
wherein the initial first power supply has a voltage level lower than a target operational supply level.

16. The apparatus of claim 15 , wherein the telemetry information includes voltage and current information.

17. The apparatus of claim 15 , wherein the portions of at least one of the first and second VRs include: an inductor; a capacitor; and switchable transistors.

18. The apparatus of claim 15 , wherein each portion of the first and second VRs is to be coupled to off-die switchable transistors, wherein the switchable transistors are coupled to an off-die inductor, and wherein the off-die inductor is coupled to an off-die capacitor.

19. An apparatus comprising:
a portion of a first voltage regulator (VR) to provide a first power supply to a first power domain;
a portion of a second VR to provide a second power supply to a second power domain separate from the first power domain;
a first one or more nodes to receive a voltage command request from a processor, wherein the voltage command request is to set a power supply delivered by at least one of the portions of the first and second VRs;
a second one or more nodes to provide telemetry information, associated with at least one of the portions of the first and second VRs, to the processor; and
one or more circuits to monitor temperature of at least one of the portions of the first and second VRs, wherein the one or more circuits is to alert the processor about the monitored temperature;

wherein the first and second power domains are part of the processor;
wherein the first VR circuitry is to provide an initial first power supply to the first power domain,
wherein the initial first power supply has a voltage level lower than a target operational supply level,
wherein the telemetry information includes voltage and current information, and the monitored temperature, and
wherein the circuitry of the first VR is to be coupled to an inductor.

20. The apparatus of claim 19 , wherein the telemetry information includes voltage and current information.

21. The apparatus of claim 19 , wherein the portions of at least one of the first and second VRs include: an inductor; a capacitor; and switchable transistors.

22. The apparatus of claim 19 , wherein each portion of the first and second VRs is to be coupled to off-die switchable transistors, wherein the switchable transistors are coupled to an off-die inductor, and wherein the off-die inductor is coupled to an off-die capacitor.

23. The apparatus of claim 19 , wherein the first VR is an integrated voltage regulator with a semiconductor die, switching elements, and magnetic components integrated into a common package.

24. A system comprising:
a processor having first and second power domains, wherein the second power domain is separate from the first power domain;
a multi-phase voltage regulator (VR) coupled to the processor, the multi-phase VR including:
a first VR to provide a first power supply to the first power domain;
a second VR to provide a second power supply to the second power domain separate from the first power domain;
an interface which is to:
receive a voltage comman

Assignees

• Intel Corp

Inventors

• Lam Son
• Koertzen Henry W
• Dibene Ii Joseph
• Patzer Steven D

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G05F1/66

  Regulating electric power · CPC title