High-voltage level-shifter circuitry

Patent metadata

Field	Value
Publication number	US-10348304-B2
Application number	US-201715714446-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 25, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

High-voltage level-shifter architectures that provide galvanic coupling between low/high-voltage domains while simultaneously enabling high speed operation, low static current consumption and high reliability under a myriad of environmental circumstances including electromagnetic interference as well as process, voltage and temperature variations.

First claim

What is claimed is:

1. A voltage level-shifter circuit comprising:
low-voltage domain circuitry configured to generate a voltage input signal with reference to a low-voltage domain ground node;
high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate a voltage output signal, with reference to a high-voltage domain common node, that corresponds to a level-shifted version of the voltage input signal;
wherein the high-voltage domain circuitry comprises charge amplifier circuitry, latch circuitry, and feedback circuitry,
wherein the charge amplifier circuitry is configured to receive as input the voltage input signal and to drive the latch circuitry to generate the voltage output signal,
wherein the feedback circuitry is configured to generate a slope detection signal in response to an erroneous condition at the latch circuitry, and
wherein the voltage level-shifter circuit further comprises common mode rejection circuitry configured to suppress propagation of a common mode error signal to the latch circuitry, wherein the common mode rejection circuitry comprises first clamp circuitry coupled to a control terminal of a first transistor of the charge amplifier circuitry and configured to pull the control terminal of the first transistor to a voltage potential of the high-voltage domain common node in response to the slope detection signal, and second clamp circuitry coupled to a control terminal of a second transistor of the charge amplifier circuitry and configured to pull the control terminal of the second transistor to the voltage potential of the high-voltage domain common node in response to the slope detection signal.

2. The voltage level-shifter circuit of claim 1 , wherein the charge amplifier circuitry comprises:
a first capacitor coupled to an output of a first inverter of the low-voltage domain circuitry,
a second capacitor coupled to an output of a second inverter of the low-voltage domain circuitry and configured to capacitively couple the high-voltage domain circuitry to the low-voltage domain circuitry;
a first transistor including a control terminal coupled to the first capacitor and a first terminal of a first resistor, a source/drain terminal coupled to a first node of the latch circuitry, and a drain/source terminal coupled to a second terminal of the first resistor and the high-voltage domain common node; and
a second transistor including a control terminal coupled to the second capacitor and a first terminal of a second resistor, a source/drain terminal coupled to a second node of the latch circuitry, and a drain/source terminal coupled to a second terminal of the second resistor and the high-voltage domain common node.

3. The voltage-level shifter circuit of claim 1 , further comprising:
overvoltage protection circuitry configured to protect the voltage level-shifter circuit from excess voltage.

4. A voltage level-shifter circuit comprising:
low-voltage domain circuitry configured to generate a voltage input signal with reference to a low-voltage domain ground node;
high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate a voltage output signal, with reference to a high-voltage domain common node, that corresponds to a level-shifted version of the voltage input signal;
wherein the high-voltage domain circuitry comprises charge amplifier circuitry and latch circuitry,
wherein the charge amplifier circuitry is configured to receive as input the voltage input signal and to drive the latch circuitry to generate the voltage output signal; and
wherein the voltage level-shifter circuit further comprises bit-mismatch corrective circuitry configured to enforce the voltage output signal to a value that corresponds to the level-shifted version of the voltage input signal, wherein the bit-mismatch corrective circuitry comprises:
sampling circuitry configured to sample the voltage output signal;
clock circuitry configured to control the sampling circuit to sample the voltage output signal at a particular rate; and
comparator circuitry configured to compare an instant logic level of the voltage input signal with a sampled logic level of the voltage output signal, and to output a bit-correction signal to the low-voltage domain circuitry to enforce the voltage output signal to the value that corresponds to the level-shifted version of the voltage input signal.

5. A voltage level-shifter circuit comprising:
low-voltage domain circuitry configured to generate a voltage input signal with reference to a low-voltage domain ground node;
high-voltage domain circuitry capacitively coupled to the low-voltage domain circuitry and configured to generate a voltage output signal, with reference to a high-voltage domain common node, that corresponds to a level-shifted version of the voltage input signal;
wherein the high-voltage domain circuitry comprises charge amplifier circuitry and latch circuitry,
wherein the charge amplifier circuitry is configured to receive as input the voltage input signal and to drive the latch circuitry to generate the voltage output signal; and
wherein the voltage level-shifter circuit further comprises phase correction circuitry configured to dampen oscillations at nodes of the latch circuitry and overvoltage protection circuitry configured to protect the voltage level-shifter circuit from excess voltage, wherein the phase correction circuitry comprises a resistor-capacitor network coupled between an output of the latch circuitry and inputs of the overvoltage protection circuitry.

6. The voltage level-shifter circuit of claim 1 , wherein the low-voltage domain circuitry comprises a first inverter coupled in series with a second inverter, and wherein the first inverter and the second inverter are configured to generate the voltage input signal.

7. The voltage level-shifter circuit of claim 1 , wherein the latch circuitry comprises a first latch inverter and a second latch inverter, wherein an output of the first latch inverter is coupled to an input of the second latch inverter at a first node of the latch circuitry, and an output of the second latch inverter is coupled to an input of the first latch inverter at a second node of the latch circuitry.

8. The voltage level-shifter circuit of claim 1 , further comprising:
buffer circuitry coupled at an input terminal to a node of the latch circuitry and configured to generate at an output terminal the voltage output signal with reference to the high-voltage domain common node.

Assignees

• Infineon Technologies Ag

Inventors

• Ullmann Igor
• Kalt Andreas
• Wachter Franz

Classifications

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title