Modulators

Patent metadata

Field	Value
Publication number	US-10348282-B1
Application number	US-201816050762-A
Country	US
Kind code	B1
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

This application relates to time-encoding modulators (TEMs). A TEM ( 100 ) receives an input signal (S IN ) and outputs a time encoded signal (S PWM ). A comparator ( 101 ) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter ( 104 ) and a delay element ( 106 ) for applying a controlled delay. In some embodiments a latching element ( 101, 302; 106, 402 ) is located within the forward signal path to synchronize any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (S OUT ) from the modulator are thus synchronized to the first clock signal. In some embodiments the delay element ( 106 ) is a digital delay element which is synchronized to the first clock signal.

First claim

The invention claimed is:

1. A time-encoding modulator comprising:
a forward signal path from a modulator input for receiving an input signal and a modulator output for outputting a time encoded signal;
a feedback path forming a feedback loop with at least part of the forward signal path;
a comparator located in the forward signal path within the feedback loop;
a filter located within the feedback loop;
a delay element for applying a controlled delay within the feedback loop; and
a latching element within the forward signal path, the latching element being configured to receive a first clock signal and to synchronise any signal transitions output from the latching element to the first clock signal such that any signal transitions in the output from the modulator are synchronised to the first clock signal;
wherein the delay element comprises a digital delay element which is synchronised to the first clock signal.

2. A time-encoding modulator as claimed in claim 1 wherein the comparator is a latched comparator comprising said latching element.

3. A time-encoding modulator as claimed in claim 1 wherein the digital delay element is in the forward signal path and is a latched digital delay element comprising said latching element.

4. A time-encoding modulator as claimed in claim 1 where the digital delay element comprises a delay element counter clocked by the first clock signal, wherein the digital delay element is configured such that, in response to a signal transition at an input to the digital delay element, the delay element counter is configured to count for a defined number of clock periods before a corresponding signal transition at an output of the digital delay element.

5. A time-encoding modulator as claimed in claim 1 where the digital delay element comprises a tapped delay line.

6. A time-encoding modulator as claimed in claim 1 further comprising a cycle period controller for controlling at least one parameter of the modulator so as to control a cycle period of the time-encoded signal.

7. A time-encoding modulator as claimed in claim 6 wherein the cycle period controller is configured to control the modulator based on the time-encoded signal.

8. A time-encoding modulator as claimed in claim 6 further comprising a time-to-digital-converter configured to receive the time-encoded signal and output a digital control signal based on the time-encoded signal, wherein the cycle period controller is configured to receive the digital control signal.

9. A time-encoding modulator as claimed in claim 6 wherein the cycle period controller is configured to control said at least one parameter of the modulator so as to maintain a cycle period of the time encoded signal within a defined range on a cycle-by-cycle basis.

10. A time-encoding modulator as claimed in claim 9 wherein the cycle period controller is configured control said at least one parameter of the modulator so as to dither the cycle period.

11. A time-encoding modulator as claimed in claim 6 wherein the time-encoding modulator is operable in a first mode with a limit cycle frequency, for a quiescent input signal, equal to a first frequency and also in a second mode with a limit cycle frequency equal to a second different frequency, and wherein the cycle period controller is operable to control the modulator parameter so as to implement the first and second modes.

12. A time-encoding modulator as claimed in claim 6 wherein the digital delay element comprises a variable delay element for applying a controllably variable delay and said at least one parameter of the modulator controlled by the timing controller comprises the delay applied by the variable delay element.

13. A time-encoding modulator as claimed in claim 12 where the digital delay element comprises:
a delay element counter clocked by the first clock signal and responsive to a signal transition at an input to the digital delay element to start counting from an initial count value; and
a digital comparator for receiving a count value from the delay element counter and triggering a signal transition at an output of the digital delay element when the count value differs from an initial count value by an amount defined by a reference value;
wherein the cycle period controller is configured to control said defined reference value.

14. A time-encoding modulator as claimed in claim 6 wherein the comparator is operable as a hysteretic comparator to apply a defined amount of hysteresis and said at least one parameter of the modulator controlled by the cycle period controller comprises the amount of hysteresis applied by the hysteretic comparator.

15. A time-encoding modulator as claimed in claim 6 further comprising a variable analogue delay element for applying a controllably variable delay and said at least one parameter of the modulator controlled by the cycle period controller comprises the delay applied by the variable analogue delay element.

16. A time-encoding modulator as claimed in claim 1 wherein the comparator is operable as a hysteretic comparator to apply a defined amount of hysteresis.

17. A time-encoding modulator as claimed in claim 1 wherein the filter is located in the feedback path and the input signal is supplied to a first input of the comparator and a filtered signal output from the filter is supplied to a second input of the comparator.

18. A time-encoding modulator as claimed in claim 17 wherein the filter comprises:
a current generator configured to receive the feedback signal and to generate a controlled current signal having a first defined current during periods of a first output state and a second defined current during periods of a second output state; and
a capacitor configured to be charged and discharged by the controlled current signal.

19. A time-encoding modulator as claimed in claim 1 wherein a feedback signal from the feedback path is combined with the input signal and filtered by the filter and a filtered signal output from the filter is supplied to a first input of the comparator to be compared to a defined reference.

20. A time-encoding modulator as claimed in claim 19 wherein the feedback path comprises at least one current generator configured to receive the feedback signal and to generate a controlled current signal having a first defined current during periods of a first output state and a second defined current during periods of a second output state, wherein said controlled current signal is combined with the input signal.

21. A modulator circuit comprising a time-encoding modulator as claimed in claim 1 and a first counter, wherein the first counter is configured to receive the time encoded signal and generate count values of the number of clock periods of a second clock signal during periods defined by the time encoded signal, wherein the second clock signal is synchronised to the first clock signal.

22. A modulator circuit comprising a time-encoding modulator as claimed in claim 1 ; and a demodulator comprising:
a numerically controlled oscillator configured to receive the time encoded signal and generate an oscillator signal with a that controllably varies based on the time encoded signal; and
a demodulator counter configured to receive the oscillator signal and count a number of oscillations of the oscillator signal in each of a succession of count periods.

23. A modulator circuit comprising a time-encoding modulator as claimed in claim 1 ; and a demodulator comprising:
a

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John Paul

Classifications

• H03M1/508 Primary

  the pulse width modulator being of the self-oscillating type · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title