Skew control

Patent metadata

Field	Value
Publication number	US-10348279-B2
Application number	US-201715593079-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	May 11, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.

First claim

What is claimed is:

1. A clock distribution network of a synchronous logic device, wherein
the synchronous logic device comprises multiple sub-circuits belonging to different clock domains,
wherein the clock distribution network comprises
a clock source operable for providing a global clock signal,
at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom;
a global skew control circuit for managing clock skew between the local clock signals;
wherein the global skew control circuit is operable for
managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and
disabling adjusting the delays of the programmable delay lines when in a locked operating mode,
wherein the synchronous logic device comprises
a management unit, in particular a power management unit, operable for selectively enabling or disabling clock domains, and
wherein the global skew control circuit is operable for
transitioning into the deskewing operating mode in response to enabling and/or disabling clock domains,
wherein the global skew control circuit is operable for
transitioning into the deskewing operating mode in response to disabling the clock domain associated with the programmable delay line causing the lowest delay among the programmable delay lines of enabled clock domains, and
further comprising at least one skew sensor adapted for generating a sensor signal indicative of a clock skew between two local clock signals,
wherein the global skew control circuit is operable for
repeatedly acquiring the sensor signal of the at least one skew sensor,
comparing sensor signals acquired at different points in time with each other, and
transitioning to the locked operating mode based on the comparison.

2. The clock distribution network according to claim 1 , wherein
the clock domains form a hierarchical structure;
wherein the global skew control circuit is operable for
determining initial operations for the delay lines for either reducing a delay caused by the respective programmable delay line or leaving the delay constant,
verifying, based on a current state of the delay lines, whether it is possible to perform the initial operations,
based on the verifying, performing a correction operation, the correction operation comprising correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks, the corrected commands including at least one control command for increasing a delay caused by a programmable delay line,
wherein the verifying comprises checking whether the control commands include at least one command destined to a programmable delay line that operates already at a minimum delay, and
wherein the programmable delay lines are operable for delaying the global clock signal or the signal derived therefrom by a number of delay increments,
wherein the command includes a positive or negative number of increments by which the delay caused by a particular programmable delay line shall be adjusted, and
wherein the correction operation comprises
checking whether all programmable delay lines controlled by the global skew control circuit can increase the respective number of delay increments; and,
if the result of the checking is that all programmable delay lines can increase the respective delay then increasing the number of increments of each determined command.

3. The clock distribution network according to claim 1 ,
wherein the correction operation comprises:
if the result of the checking is that at least one programmable delay line cannot increase the number of delay increments then iteratively determining corrected commands for each programmable delay line controlled by the global skew control circuit starting with a programmable delay line associated with a clock domain located at the bottom of the hierarchical structure, and
wherein the synchronous logic device comprises a microprocessor and wherein the sub-circuits comprise at least one of
a processor core including a first level cache,
a second level cache, or
a third level cache.

Assignees

• IBM

Inventors

• Arp Andreas
• Cilek Fatih
• Koch Michael
• Ringe Matthias

Classifications

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title