Light emitting element array and optical transmission device

US10348059B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10348059-B2
Application numberUS-201715631378-A
CountryUS
Kind codeB2
Filing dateJun 23, 2017
Priority dateAug 10, 2016
Publication dateJul 9, 2019
Grant dateJul 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A light emitting element array includes plural semiconductor stacking structures and a light screening portion. The plural semiconductor stacking structures each include a light emitting portion and a light receiving portion that receives light propagated in a lateral direction via a semiconductor layer from the light emitting portion. The light screening portion is provided between the plural semiconductor stacking structures to screen light directed from the light emitting portion of one of the semiconductor stacking structures to the light receiving portion of another semiconductor stacking structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting element array comprising: a plurality of semiconductor stacking structures each including a light emitting portion and a light receiving portion configured to receive light propagated in a lateral direction via a semiconductor layer from the light emitting portion; and a light screening wall provided between the plurality of semiconductor stacking structures configured to screen light directed from the light emitting portion of one of the semiconductor stacking structures to the light receiving portion of another semiconductor stacking structure, wherein the light emitting portion comprises a lower reflector, an active region, and an upper reflector that are commonly formed with a lower reflector, an active region, and an upper reflector of the light receiving portion, respectively, wherein the active region of the light emitting portion and the active region of the light receiving portion are continuously formed without a layer interposed therebetween, and wherein the light emitting portion and the light receiving portion are formed as a single mesa structure; wherein each of the plurality of semiconductor stacking structures includes a semi-insulating substrate, and wherein the light emitting portion, the light receiving portion, an anode electrode pad connected to the light emitting portion, a cathode electrode pad connected to the light emitting portion, an anode electrode pad connected to the light receiving portion, and a cathode electrode pad connected to the light emitting portion are formed on a front surface side of the semi-insulating substrate. 2. The light emitting element array according to claim 1 , wherein the light screening wall is constituted of a semiconductor layer that is common with a semiconductor layer that constitutes the plurality of semiconductor stacking structures. 3. The light emitting element array according to claim 1 , wherein the active region of the light emitting portion is configured to implement a light emitting function of the light emitting portion, and a height of the light screening wall in a stacking direction of the plurality of semiconductor stacking structures is equal to or more than a height of the active region of the light emitting portion in the stacking direction of the plural semiconductor stacking structures. 4. The light emitting element array according to claim 1 , wherein a height of the light screening wall in a stacking direction of the plurality of semiconductor stacking structures is equal to or more than half a height of the plurality of semiconductor stacking structures. 5. The light emitting element array according to claim 1 , wherein a light screening layer is formed on a surface of the light screening wall. 6. The light emitting element array according to claim 1 , wherein the light receiving portion includes a current-voltage conversion unit configured to convert a current generated when the light receiving portion receives the light propagated in the lateral direction into a voltage. 7. The light emitting element array according to claim 1 , wherein a length of the light screening wall as viewed in plan is larger than a length of the light emitting portion as viewed in plan or a length of the light receiving portion as viewed in plan. 8. The light emitting element array according to claim 1 , wherein a length of the light screening wall as viewed in plan is larger than a total of a length of the light emitting portion as viewed in plan and a length of the light receiving portion as viewed in plan. 9. The light emitting element array according to claim 1 , wherein the light screening wall is provided so as to surround each of the plurality of semiconductor stacking structures. 10. An optical transmission device comprising: the light emitting element array according to claim 1 ; a modulation unit configured to modulate light from the plurality of light emitting portions; and a plurality of optical fibers configured to transmit emitted light modulated by the modulation unit and emitted from each of the plurality of light emitting portions. 11. The light emitting element array according to claim 1 , wherein a current interrupting region is formed between the upper reflector of the light emitting portion and the upper reflector of the light receiving portion. 12. The light emitting element array according to claim 1 , wherein a height of the light screening wall in a stacking direction of the plurality of semiconductor stacking structures is less than a height of the plurality of semiconductor stacking structures. 13. The light emitting element array according to claim 1 , wherein the lower reflector of the light emitting portion comprises a same semiconductor layer as the lower reflector of the light receiving portion, wherein the active region of the light emitting portion comprises a same semiconductor layer as the active region of the light receiving portion, and wherein the upper reflector of the light emitting portion comprises a same semiconductor layer as the upper reflector of the light receiving portion. 14. The light emitting element array according to claim 1 , wherein the light screening wall is formed in an area other than an area in which the anode electrode pads and the cathode electrode pads are formed. 15. The light emitting element array according to claim 1 , wherein the anode electrode pad connected to the light emitting portion, the cathode electrode pad connected to the light emitting portion, the anode electrode pad connected to the light receiving portion, and the cathode electrode pad connected to the light emitting portion are directly formed on the semi-insulating substrate. 16. The light emitting element array according to claim 1 , wherein the light emitting portion and the light receiving portion each have a rectangular shape, and wherein a width of a coupling portion connecting the light emitting portion with the light receiving portion is smaller than widths of remaining portions of the light emitting portion and the light receiving portion.

Assignees

Inventors

Classifications

  • having positive and negative electrodes on the same side of the substrate · CPC title

  • characterised by the configuration · CPC title

  • comprising arrays of active devices and fibres · CPC title

  • Structure being part of a DBR (H01S5/18391 takes precedence) · CPC title

  • Photo-diodes, e.g. transceiver devices, bidirectional devices (H01S5/0265 takes precedence) · CPC title

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What does patent US10348059B2 cover?
A light emitting element array includes plural semiconductor stacking structures and a light screening portion. The plural semiconductor stacking structures each include a light emitting portion and a light receiving portion that receives light propagated in a lateral direction via a semiconductor layer from the light emitting portion. The light screening portion is provided between the plural …
Who is the assignee on this patent?
Fuji Xerox Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01S5/423. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).