Methods of forming source/drain regions on FinFET devices

Patent metadata

Field	Value
Publication number	US-10347748-B2
Application number	US-201615092168-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Apr 6, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

First claim

What is claimed:

1. A method of forming a source/drain region on a FinFET device, comprising:
forming a plurality of fin-formation recesses to define a fin in a semiconductor substrate;
forming a layer of insulating material in said plurality of fin-formation recesses;
forming a gate structure around said fin;
after forming said gate structure, forming a final source/drain cavity in said fin, said final source/drain cavity comprising an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of said gate structure, wherein said lower innermost edge extends laterally further under said gate structure than does said upper innermost edge, and wherein a height level of a bottom of said final source/drain cavity is below a height level of an upper surface of said layer of insulating material relative to an upper surface of said fin; and
after forming said final source/drain cavity, performing an epitaxial growth process to form an epi semiconductor material in said final source/drain cavity.

2. The method of claim 1 , wherein forming said final source/drain cavity in said fin comprises:
performing at least one etching process to define an initial cavity in said fin;
performing an amorphization implant process to form a region of amorphous fin material in said fin at a bottom of said initial cavity; and
performing an isotropic etching process to remove at least a portion of said amorphous fin material and thereby define said final source/drain cavity.

3. The method of claim 1 , wherein forming said gate structure comprises forming a gate insulation layer, a gate electrode, a gate cap and at least one sidewall spacer.

4. The method of claim 1 , wherein forming said final source/drain cavity in said fin comprises:
performing a first anisotropic etching process to define a first cavity in said fin;
performing a second isotropic etching process on said first cavity so as to define a second cavity in said fin;
performing an amorphization implant process to form a region of amorphous fin material in said fin at a bottom of said second cavity; and
performing a third isotropic etching process to remove at least a portion of said amorphous fin material and thereby define said final source/drain cavity.

5. The method of claim 4 , wherein said first cavity is substantially self-aligned with an outermost edge of said gate structure.

6. The method of claim 5 , wherein performing said second isotropic etching process comprises performing said second isotropic etching process so as to define said second cavity having a first peak depth.

7. The method of claim 6 , wherein performing said third isotropic etching process comprises performing said third isotropic etching process to define said final source/drain cavity having a second peak depth that is greater than said first peak depth.

8. The method of claim 1 , wherein said epi semiconductor material comprises one of silicon, silicon-germanium, silicon carbon, or germanium.

9. The method of claim 2 , wherein performing said amorphization implant process comprises performing said amorphization implant process using an ion dose that falls within a range of about 1×10 14 -5×10 15 ions/cm 2 at an energy level that falls within a range of about 2-50 keV.

10. The method of claim 9 , wherein said amorphization implant process is performed using one of xenon, antimony, argon, germanium, silicon, or GeF 2 .

11. The method of claim 1 , wherein said upper innermost edge is located at a first level positioned a first distance beneath an upper surface of said fin and said lower innermost edge is located at a second level positioned a second distance beneath said upper surface of said fin, said second distance being greater than said first distance.

12. The method of claim 2 , wherein, after performing said at least one etching process, a height level of a bottom of said initial cavity is below said height level of said upper surface of said layer of insulating material relative to said upper surface of said fin.

13. The method of claim 2 , wherein, after performing said at least one etching process, a height level of a bottom of said initial cavity is above said height level of said upper surface of said layer of insulating material relative to said upper surface of said fin.

14. The method of claim 4 , wherein, after performing said second isotropic etching process, a height level of a bottom of said second cavity is below said height level of said upper surface of said layer of insulating material relative to said upper surface of said fin.

15. The method of claim 4 , wherein, after performing said second isotropic etching process, a height level of a bottom of said second cavity is above said height level of said upper surface of said layer of insulating material relative to said upper surface of said fin.

16. A method of forming a source/drain region on a FinFET device, comprising:
forming a plurality of fin-formation recesses to define a fin in a semiconductor substrate;
forming a layer of insulating material in said plurality of fin-formation recesses;
forming a gate structure around said fin;
after forming said gate structure, forming a source/drain cavity by:
performing a first anisotropic etching process to define a first cavity in said fin;
performing a second isotropic etching process on said first cavity so as to define a second cavity in said fin;
performing an amorphization implant process to form a region of amorphous fin material in said fin at a bottom of said second cavity; and
performing a third isotropic etching process to remove at least a portion of said amorphous fin material and thereby define said source/drain cavity, wherein, after performing said third isotropic etching process, a height level of a bottom of said source/drain cavity is below a height level of an upper surface of said layer of insulating material relative to an upper surface of said fin; and
performing an epitaxial growth process to form an epi semiconductor material in said source/drain cavity.

17. The method of claim 16 , wherein said first cavity is substantially self-aligned with an outermost edge of said gate structure.

18. The method of claim 16 , wherein performing said second isotropic etching process comprises performing said second isotropic etching process so as to define a second cavity having a first peak depth and a first innermost edge, said first innermost edge extending under at least a portion of said gate structure.

19. The method of claim 18 , wherein performing said third isotropic etching process comprises performing said third isotropic etching process to define a source/drain cavity comprising a second peak depth and a second innermost edge for said source/drain cavity, wherein said second innermost edge extends under at least a portion of said gate structure for a greater distance than does said first innermost edge and said second peak depth is greater than said first peak depth.

20. The method of claim 19 , wherein said first innermost edge is located at a first level positioned a first distance beneath an upper surface of said fin and said second innermost edge is located at a second level positioned a second distance beneath said upper surface of said fin, said second distance being greater than said first distance.

21. The method of claim 16 , wherein performing said amorphization implant process comprises performing said amorphization implant process using an ion dose that falls within a

Assignees

• Globalfoundries Inc

Inventors

• Pandey Shesh Mani
• Rahman Muhammad
• Samavedam Srikanth Balaji

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H01L21/306

  Electricity · mapped topic

• H01L29/66795 Primary

  Electricity · mapped topic

• H01L21/265

  Electricity · mapped topic