Semiconductor chip using logic circuitry including complementary FETs for reverse engineering protection

Patent metadata

Field	Value
Publication number	US-10347630-B2
Application number	US-201615135610-A
Country	US
Kind code	B2
Filing date	Apr 22, 2016
Priority date	Apr 28, 2014
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

First claim

What is claimed is:

1. A logic gate for implementing a logical function comprising:
a tie cell circuit comprising
at least one p channel field effect transistor;
at least one n channel field effect transistor;
a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and
a second power supply terminal configured to receive a second supply voltage with a lower supply potential;
wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that
the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and
the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;

wherein the tie cell circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the tie cell circuit; and

a logic circuit configured to implement the logical function of the logic gate and having a supply terminal coupled to the gate of the at least one p channel field effect transistor or the gate of the at least one n channel field effect transistor.

2. The logic gate according to claim 1 , wherein the logic circuit comprises a first supply terminal and a second supply terminal, wherein the first supply terminal is coupled to the gate of the at least one p channel field effect transistor and the second supply terminal is coupled to the gate of the at least one n channel field effect transistor.

3. The logic gate according to claim 1 , wherein the tie cell circuit comprises:
a plurality of p channel field effect transistors;
wherein the plurality of p channel field effect transistors and the at least one n channel field effect transistor are connected such that
the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gates of the plurality of p channel field effect transistors; and
the plurality of p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gate of the at last one n channel field effect transistor;

wherein the tie cell circuit is configured such that the logic state of the gates of the plurality of p channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the tie cell circuit; and
wherein the gates of the plurality of p channel field effect transistors or the gate of the at least one n channel field effect transistor are coupled to the supply terminal of the logic circuit.

4. The logic gate according to claim 1 , wherein the tie cell circuit comprises:
a plurality of n channel field effect transistors;
wherein the plurality of n channel field effect transistors and the at least one p channel field effect transistor are connected such that
the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the higher supply potential to the gates of the plurality of n channel field effect transistors; and
the plurality of n channel field effect transistors, if supplied with the higher supply potential at their gates, supply the lower supply potential to the gate of the at last one p channel field effect transistor;

wherein the tie cell circuit is configured such that the logic state of the gates of the plurality of n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the tie cell circuit; and
wherein the gates of the plurality of n channel field effect transistors or the gate of the at least one p channel field effect transistor are coupled to the supply terminal of the logic circuit.

5. The logic gate according to claim 1 , wherein the logic circuit comprises a combinatorial logic gate.

6. The logic gate according to claim 1 , wherein the logic circuit comprises a sequential logic gate.

7. The logic gate according to claim 1 , further comprising:
a source of the at least one p channel field effect transistor connected to the first power supply terminal;
a source of the at least one n channel field effect transistor connected to the second power supply terminal;
the gate of the at least one p channel field effect transistor connected to a drain of the at least one n channel field effect transistor; and
the gate of the at least one n channel field effect transistor connected to a drain of the at least one p channel field effect transistor.

8. The logic gate according to claim 1 , wherein the tie cell circuit comprises a high capacitance tie cell circuit.

9. The logic gate according to claim 1 , wherein the tie cell circuit comprises:
a plurality of p channel field effect transistors;
a plurality of n channel field effect transistors;
wherein the plurality of p channel field effect transistors and the plurality of n channel field effect transistors are connected such that
the plurality of n channel field effect transistors, if supplied with the upper supply potential at their gates, supply the lower supply potential to the gates of the plurality of p channel field effect transistors; and
the plurality of p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gates of the plurality of n channel field effect transistors;

wherein the tie cell circuit is configured such that the logic state of the gates of the plurality of p channel field effect transistors and the logic state of the gates of the plurality of n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the tie cell circuit; and
wherein the gates of the plurality of p channel field effect transistors or the gates of the plurality of n channel field effect transistors are coupled to the supply terminal of the logic circuit.

10. The logic gate according to claim 9 , wherein the plurality of p channel field effect transistors are connected in series and their gates are connected and the plurality of n channel field effect transistors are connected in series and their gates are connected.

11. A semiconductor chip, comprising a multiplicity of logic gates, each of the multiplicity of logic gates comprising the logic gate of claim 1 .

12. The semiconductor chip of claim 11 , wherein the logical functions of each of the multiplicity of logic gates are at least partially different.

Assignees

• Infineon Technologies Ag

Inventors

• Kuenemund Thomas

Classifications

• H10W42/405

  using active circuits · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L23/576

  Electricity · mapped topic

• H03K19/215

  using field-effect transistors · CPC title