Through-substrate-vias with self-aligned solder bumps

Patent metadata

Field	Value
Publication number	US-10347600-B2
Application number	US-201715813222-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	May 9, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a base substrate, a carrier substrate, and a buried metallization layer intermediate the base substrate and the carrier substrate, and a top metallization layer of a first conductive metal material on a top surface of the carrier substrate;
forming unfilled through-substrate-vias in the carrier substrate to the buried metallization layer;
forming an under bump metallization layer of a second conductive metal material on surfaces defining the unfilled through-substrate-vias, a perimeter surrounding the unfilled through-substrate-vias on the carrier substrate, and on the first conductive metal material layer, wherein the under bump metallization layer is coupled to the buried metallization layer and the top metallization layer, and wherein the first and second conductive metal materials are different;
depositing and patterning a sacrificial layer to form openings exposing the unfilled through-substrate-vias, the perimeter surrounding the unfilled through-substrate-vias on the carrier substrate, and on the top metallization layer;
filling the openings with a third conductive metal material to form filled through-sub strate-vias; and
removing the sacrificial layer to form cylindrical shaped solder bumps self-aligned to the filled through-substrate-vias.

2. The method of claim 1 , wherein the filled through-substrate-vias have an aspect ratio relative to the carrier substrate of less than 10.

3. The method of claim 1 , wherein the first and third conductive metal materials are the same.

4. The method of claim 1 , further comprising reflowing the third conductive metal material to form hemispherical-shaped solder bumps self-aligned to a filled through-substrate-via.

5. The method of claim 1 , wherein depositing the sacrificial layer comprises laminating a dry photoresist.

6. The method of claim 1 , wherein forming the under bump metallization layer comprises depositing a dry photoresist over topography provided on the carrier substrate, patterning the dry photoresist so as to expose surfaces corresponding to the unfilled through-substrate-vias and at least a portion of the perimeter surrounding the unfilled through-substrate-vias on the carrier substrate and on the metallization layer, sputter depositing the second conductive metal material onto the exposed surfaces, and removing the dry photoresist with a lift off process.

7. The method of claim 1 , wherein the first, second and third conductive metal material are superconducting metals.

8. The method of claim 1 , wherein providing the base substrate bonded to the carrier substrate comprising the buried metallization layer intermediate the base substrate and the carrier substrate comprises applying a thermocompression bonding force and temperature to bond the base substrate and the carrier substrate, wherein each of the base substrate and the carrier substrate include a portion of buried metallization layer.

9. The method of claim 1 , wherein filling the openings with the third conductive metal material comprises an injection molding soldering process or an electroplating process.

10. The method of claim 1 , wherein the carrier substrate has a thickness defining a length dimension of the through-substrate-via.

11. The method of claim 10 , further comprising thinning the carrier substrate to define the thickness prior to forming unfilled through-substrate-vias.

Assignees

• IBM

Inventors

• Abraham David W
• Cotte John M

Classifications

• H10W99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/731

  of die-attach connectors · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title