Cell contact

Patent metadata

Field	Value
Publication number	US-10347487-B2
Application number	US-201715812274-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Nov 14, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

First claim

What is claimed is:

1. A method comprising:
forming a resist underlayer on a dielectric spacer, the dielectric spacer formed on a structure for a cell contact, the structure including a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region formed on a dielectric region above a substrate, material of the silicon-rich dielectric anti-reflective coating region being different from material of the dielectric region;
processing the resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region such that an array of columns is formed in the dielectric region; and
filling regions between the columns of the array of columns with conductive material, forming the cell contact.

2. A method comprising:
forming a resist underlayer on a dielectric spacer, the dielectric spacer formed on a structure for a cell contact, the structure including a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region formed on a dielectric region above a substrate;
processing the resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region such that an array of columns is formed in the dielectric region; and
filling regions between the columns of the array of columns with conductive material, forming the cell contact, wherein processing the resist underlayer, the dielectric spacer, the silicon-rich dielectric anti-reflective coating, and the dielectric region includes forming each column with a cap region, the cap region containing remaining portions of the silicon-rich dielectric anti-reflective coating.

3. The method of claim 2 , wherein forming each column with a cap region includes forming each column from material of the dielectric region.

4. The method of claim 3 , wherein the material of the dielectric region includes diamond-like carbon.

5. The method of claim 1 , wherein the pattern area of pillars includes diamond-like carbon.

6. The method of claim 1 , wherein the silicon-rich dielectric anti-reflective coating includes one or more materials selected from a group of materials including a silicon-rich oxide, a silicon-rich nitride, and a silicon-rich oxynitride.

7. A method comprising:
forming a resist underlayer on a dielectric spacer, the dielectric spacer formed on a structure for a cell contact, the structure including a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region formed on a dielectric region above a substrate;
processing the resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region such that an array of columns is formed in the dielectric region; and
filling regions between the columns of the array of columns with conductive material, forming the cell contact, wherein the processing includes forming the array of columns with a pitch that is half the pitch of the patterned area of pillars.

8. The method of claim 1 , wherein forming the resist underlayer on the dielectric spacer includes forming the resist underlayer on an oxide region formed as the dielectric spacer.

9. The method of claim 8 , wherein the oxide region includes silicon oxide.

10. The method of claim 1 , wherein the method includes, prior to forming the resist underlayer, forming the dielectric spacer on the patterned area of pillars and on a region adjacent the patterned area, the region adjacent the patterned area terminating the patterned area.

11. A method comprising:
forming a resist underlayer on a dielectric spacer, the dielectric spacer formed on a structure for a cell contact, the structure including a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region formed on a dielectric region above a substrate;
processing the resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region such that an array of columns is formed in the dielectric region; and
filling regions between the columns of the array of columns with conductive material, forming the cell contact, wherein the method includes forming the array of columns in the dielectric region by reducing the silicon-rich dielectric anti-reflective coating region to have columns of silicon-rich dielectric anti-reflective coating on the reduced silicon-rich dielectric anti-reflective coating region, forming a chop mask on a portion of the reduced silicon-rich dielectric anti-reflective coating region, removing portions of the reduced silicon-rich dielectric anti-reflective coating region adjacent the chop mask, and removing portions of the dielectric region forming the array of columns adjacent the remaining dielectric region.

12. The method of claim 11 , wherein removing portions of the dielectric region forming the array of columns in the dielectric region includes forming the array of columns in the dielectric region adjacent material of the dielectric region below the chop mask and removing material of the dielectric region from between the columns with the columns extending to a base dielectric on which the dielectric region was formed.

13. The method of claim 12 , wherein the base dielectric includes tetraethyl orthosilicate.

14. The method of claim 13 , where the tetraethyl orthosilicate is formed on a spin-out dielectric disposed above a substrate.

15. A method comprising:
forming a resist underlayer on a dielectric spacer, the dielectric spacer formed on a structure for a cell contact, the structure including a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region formed on a dielectric region, the dielectric region formed on a base dielectric region above a substrate;
etching back the resist underlayer and the dielectric spacer forming an etched back structure having a surface that terminates and exposes the pillars and remaining portions of the dielectric spacer and resist underlayer between the pillars, with the patterned area of pillars adjacent a terminating dielectric region that terminates the pattern area;
stripping the etched back structure such that only portions of the remaining portions of the dielectric spacer are arranged as columns of dielectric spacer on the silicon-rich dielectric anti-reflective coating region;
dry etching the columns of dielectric spacer and recessing the silicon-rich dielectric anti-reflective coating region;
reducing the dry etched columns of dielectric spacer and recessed silicon-rich dielectric anti-reflective coating region forming columns of silicon-rich dielectric anti-reflective coating on the reduced recessed silicon-rich dielectric anti-reflective coating region;
forming a chop mask on a portion of the reduced recessed silicon-rich dielectric anti-reflective coating region; and
dry etching the dielectric region with the columns of silicon-rich dielectric anti-reflective coating on the reduced recessed silicon-rich dielectric anti-reflective coating region adjacent the chop mask, forming an array of columns on the base dielectric region above the substrate.

16. The method of claim 15 , wherein forming the array of columns on the base dielectric region above the substrate includes maintaining a portion of the columns of silicon-rich dielectric anti-reflective coating as caps on the columns of the array of columns.

17. The method of claim 15 , wherein the method includes filling regions between

Assignees

• Micron Technology Inc

Inventors

• Lee Che-Chi
• Oshima Hiromitsu

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title