Memory system having impedance calibration circuit

Patent metadata

Field	Value
Publication number	US-10347358-B2
Application number	US-201815968065-A
Country	US
Kind code	B2
Filing date	May 1, 2018
Priority date	Sep 11, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A memory system includes: a buffer memory device; and a memory controller configured to communicate data with the buffer memory device, wherein the memory controller includes: an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage; and an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal.

First claim

What is claimed is:

1. A memory system comprising:
a buffer memory device; and
a memory controller configured to communicate data with the buffer memory device,
wherein the memory controller includes:
an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage;
a reference voltage generating unit configured to generate a reference voltage; and
an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal, based on the reference voltage,
wherein the reference voltage generating unit includes:
a resistor ladder including a plurality of resistors coupled in series between the input/output power voltage and a ground voltage;
a pre-reference voltage generating unit configured to generate a pre-reference voltage;
a comparator configured to compare any one of a plurality of division voltages with the pre-reference voltage; and
a first transistor coupled between the input/output power voltage and the resistor ladder, the first transistor being controlled by an output of the comparator.

2. The memory system of claim 1 ,
wherein the resistor ladder generates the plurality of division voltages that have voltage levels different from one another, and
wherein the plurality of division voltages include a plurality of first division voltages included in a first reference voltage range and a plurality of second division voltages included in a second reference voltage range that is lower than the first reference voltage range.

3. The memory system of claim 2 , wherein the reference voltage generating unit includes:
a first reference voltage selector configured to output a first mode reference voltage by selecting any one of the plurality of first division voltages;
a second reference voltage selector configured to output a second mode reference voltage by selecting any one of the plurality of second division voltages; and
a mode selector configured to select any one of the first mode reference voltage and the second mode reference voltage in response to a mode selection signal and output the selected voltage as the reference voltage.

4. The memory system of claim 3 , further comprising a calibration resistor terminated to the input/output power voltage,
wherein the reference voltage has a voltage level equal to that of the first mode reference voltage.

5. The memory system of claim 3 , further comprising a calibration resistor terminated to the ground voltage,
wherein the reference voltage has a voltage level equal to that of the second mode reference voltage.

6. The memory system of claim 1 , wherein the first signal is activated when the input/output power voltage is decreased to a certain level or lower.

7. The memory system of claim 1 , wherein the input/output power voltage sensor generates a first voltage changed in response to the change in input/output power voltage, and generates the first signal by comparing the first voltage to the reference voltage.

8. The memory system of claim 7 , wherein the input/output power voltage sensor includes:
the resistor ladder configured to include the plurality of resistors coupled in series, and generate the plurality of division voltages having voltage levels different from one another; and
an input/output power voltage selector configured to output the first voltage by selecting any one of the plurality of division voltages.

9. A memory controller comprising:
a reference voltage generating unit configured to generate a reference voltage;
an input/output power voltage sensor configured to generate an input/output power voltage change flag signal activated when an input/output power voltage is decreased to a certain level or lower, based on the reference voltage; and
an impedance calibration circuit configured to start an impedance calibration operation in response to the input/output power voltage change flag signal,
wherein the input/output power voltage sensor includes:
a first resistor ladder configured to include a plurality of resistors coupled in series, and generate a plurality of power division voltages having voltage levels different from one another; and
a comparator configured to generate the input/output power voltage change flag signal by comparing any one of the plurality of power division voltages to the reference voltage.

10. The memory controller of claim 9 , wherein the reference voltage generating unit includes a second resistor ladder including a plurality of resistors coupled in series between the input/output power voltage and a ground voltage,
wherein the second resistor ladder generates a plurality of reference division voltages having voltage levels different from one another, and
wherein the plurality of reference division voltages include a plurality of first division voltages included in a first reference voltage range and a plurality of second division voltages included in a second reference voltage range that is lower than the first reference voltage range.

11. The memory controller of claim 10 , wherein the reference voltage generating unit includes:
a first reference voltage selector configured to output a first mode reference voltage by selecting any one of the plurality of first division voltages;
a second reference voltage selector configured to output a second mode reference voltage by selecting any one of the plurality of second division voltages; and
a mode selector configured to select any one of the first mode reference voltage and the second mode reference voltage in response to a mode selection signal and output the selected voltage as the reference voltage.

12. A memory system comprising:
a buffer memory device including a dynamic random access memory (DRAM);
a memory controller configured to perform a data output operation of outputting data to the DRAM; and
a calibration resistor coupled to the memory controller,
wherein the memory controller includes:
a reference voltage generating unit configured to generate a first mode reference voltage and a second mode reference voltage lower than the first mode reference voltage, and generate a reference voltage by selecting any one of the first mode reference voltage and the second mode reference voltage, based on a mode selection signal;
an input/output power voltage sensor configured to generate a first signal activated when an input/output power voltage is decreased to a certain level or lower, based on the reference voltage, while the data output operation is being performed; and
an impedance calibration circuit configured to perform an impedance calibration operation, based on the calibration resistor and the reference voltage, and start the impedance calibration operation in response to the first signal,
wherein the input/output power voltage sensor includes:
a resistor ladder configured to include a plurality of resistors coupled in series, and generate a plurality of division voltages having voltage levels different from one another;
an input/output power voltage selector configured to output a first voltage by selecting any one of the plurality of division voltages; and
a comparator configured to output the first signal by comparing the first voltage to the reference voltage.

13. The memory system of claim 12 , wherein the calibration resistor is terminated to a ground voltage, and
the reference voltage generating unit selects the second mode reference voltage, based on the mode selection signal.

14. The memory system of claim 13 , wherein the reference voltage has a level lower than that of a half of the input/output power v

Assignees

• Sk Hynix Inc

Inventors

• Kim Hee Jun
• Hwang Minsoon

Classifications

• H03H11/28

  Impedance matching networks · CPC title

• G11C29/50008 Primary

  of impedance · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title