Method and device for fail-safe erase of flash memory

Patent metadata

Field	Value
Publication number	US-10347349-B2
Application number	US-201615233738-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Aug 17, 2015
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

The present disclosure provides a flash memory device including a flash memory comprising a plurality of nonvolatile memory cells, divided into a plurality of erase units; a memory section dedicated to storing erase status information, the erase status information indicating an erase status of the plurality of erase units; and a memory controller configured to receive an erase request indicating at least one erase unit; store erase status information for the at least one erase unit in the memory section; perform an erase operation on the at least one erase unit; and update the stored erase status information upon completion of the erase operation. In addition, the present disclosure provides a way how incomplete erase commands can be handled transparently in a fail safe way.

First claim

The invention claimed is:

1. A method of operating a flash memory device comprising a plurality of nonvolatile memory cells, the method comprising:
receiving a first request from an external host indicating a first unit that includes a fixed number of nonvolatile memory cells, wherein the first request is one of a read request or a programming/write request; and
determining, based on stored erase status information for a first erase unit indicating an incompletely-erased erase unit, that the first erase unit corresponding to the first unit has not been completely erased, wherein the stored erase status information is included in a memory of the flash memory device.

2. The method of claim 1 , wherein the memory that stores the stored erase status information comprises a nonvolatile memory that includes the plurality of nonvolatile memory cells.

3. The method of claim 1 , further comprising returning a signal indicating a program state for the incompletely-erased erase unit, wherein the first unit comprises at least one read unit or programming/write unit.

4. The method of claim 3 , wherein determining that the first erase unit corresponding to the first unit has not been completely erased comprises:
mapping the at least one read unit or programming/write unit to the first erase unit; and
reading the stored erase status information associated with the mapped first erase unit.

5. The method of claim 3 , further comprising upon determining that the first erase unit has not been completely erased, scheduling the incompletely-erased erase unit for an erase operation.

6. The method of claim 3 , further comprising receiving an erase request indicating the incompletely-erased erase unit in response to the returned signal.

7. The method of claim 6 , further comprising completing the erase operation on the incompletely-erased erase unit during an idle state of the flash memory device.

8. The method of claim 1 , further comprising:
receiving an erase request from the external host that indicates at least one erase unit;
storing erase status information for the at least one erase unit in the memory of the flash memory device, wherein the erase status information indicates a pending erase request for the at least one erase unit; and
performing an erase operation on the at least one erase unit, wherein, upon completion of the erase operation, the erase status information is updated to indicate that the at least one erase unit is completely erased.

9. The method of claim 8 , wherein storing the erase status information comprises setting a flag indicating a pending erase operation for the at least one erase unit in the memory.

10. The method of claim 9 , further comprising
setting a further flag indicating completion of the erase operation for the at least one erase unit in the memory; or
resetting the flag indicating the pending erase operation for the at least one erase unit in the memory.

11. The method of claim 8 , wherein storing the erase status information comprises:
storing mapping information for the at least one erase unit in the memory; and
erasing the mapping information.

12. A flash memory device comprising:
a flash memory comprising a plurality of nonvolatile memory cells divided into a plurality of erase units;
a memory section configured to store stored erase status information that indicates erase statuses of the plurality of erase units; and
a memory controller configured to:
receive a first request from an external host indicating a first unit that includes a fixed number of nonvolatile memory cells in the flash memory, wherein the first request is one of a read request or a programming/write request; and
determine, based on a first portion of the stored erase status information, for a first erase unit in the plurality of erase units, that indicates an incompletely-erased erase unit, that the first erase unit corresponding to the first unit has not been completely erased.

13. The flash memory device of claim 12 , wherein the memory section comprises part of the flash memory.

14. The flash memory device of claim 13 , wherein the flash memory comprises a first section comprising a first part of the plurality of nonvolatile memory cells, and a spare section comprising a second part of the plurality of nonvolatile memory cells, and wherein the memory section comprises part of the spare section.

15. The flash memory device of claim 12 , wherein the memory controller comprises a memory unit, and the memory section comprises part of the memory unit.

16. The flash memory device of claim 12 ,
wherein the memory controller comprises a firmware unit, and the firmware unit comprises a flash translation layer; and
wherein the firmware unit is configured to:
receive an erase request indicating at least one erase unit;
store erase status information for the at least one erase unit in the memory section;
perform an erase operation on the at least one erase unit; and
update the stored erase status information upon completion of the erase operation.

17. The flash memory device of claim 12 , wherein the memory controller is further configured to:
return a signal indicating a program state for the incompletely-erased erase unit corresponding to the first unit, and
wherein the signal further indicates that the incompletely-erased erase unit is to be fully programmed.

Assignees

• Harman Becker Automotive Systems Gmbh

Inventors

• Kirchner Daniel

Classifications

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C16/3445 Primary

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title