Apparatuses and methods for providing driving signals in semiconductor devices

Patent metadata

Field	Value
Publication number	US-10347321-B1
Application number	US-201815881200-A
Country	US
Kind code	B1
Filing date	Jan 26, 2018
Priority date	Jan 26, 2018
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory cell mats each including a plurality of word lines; and
a word line driver coupled to the plurality of word lines of the plurality of memory cell mats, the word line driver configured, responsive to a row active command, to:
provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats;
provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats; and
provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats; and

a control circuit configured to receive a float enable signal and a memory mat activation signal, and further configured to provide an active enable signal to the word line driver responsive to an active float enable signal and inactive memory mat activation signal, to cause the word line driver to provide no voltage.

2. The apparatus of claim 1 , wherein the word line driver is further configured, responsive to a precharge command, to provide no voltage to the selected word line and the unselected word lines of the selected memory cell mat of the plurality of memory cell mats.

3. The apparatus of claim 2 , wherein the word line driver is further configured, responsive to the precharge command, to provide the second voltage to the selected word line of the plurality of word lines of the selected memory cell mat of the plurality of memory cell mats before providing no voltage to the selected word line of the plurality of word lines of the selected memory cell mat of the plurality of memory cell mats.

4. The apparatus of claim 1 , wherein the word line driver is further configured, responsive to the row active command, to provide the second voltage to the selected word line of the plurality of word lines of the selected memory cell mat of the plurality of memory cell mats before providing the first voltage to the selected word line of the plurality of word lines of the selected memory cell mat of the plurality of memory cell mats.

5. The apparatus of claim 1 , wherein the word line driver is configured, responsive to the row active command in a first operation mode, to:
provide the first voltage to the selected word line of the plurality of the word lines of the selected memory cell mat of the plurality of memory cell mats;
provide the second voltage to each of the unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats; and
provide no voltage to each of the plurality of word lines of each of the unselected memory cell mats of the plurality of memory cell mats; and
wherein the word line driver is further configured, responsive to the row active command in a second operation mode, to:
provide the first voltage to the selected word line of the plurality of the word lines of the selected memory cell mat of the plurality of memory cell mats; and
provide the second voltage to each of the unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats; and
provide the second voltage to each of the plurality of word lines of each of the unselected memory cell mats of the plurality of memory cell mats.

6. An apparatus, comprising:
a memory mat including a main word line and a plurality of subword lines;
a plurality of subword drivers coupled to the main word line, each subword driver of the plurality of subword drivers coupled to a respective one of the plurality of subword lines and configured to receive a respective driving signal, when activated each subword driver of the plurality of subword drivers configured to drive the respective one of the plurality of subword lines to a voltage of the respective driving signal; and
a driving signal driver configured to provide the respective driving signals to the plurality of subword drivers, the driving signal driver configured to provide the respective driving signals having a first voltage or a second voltage when the memory mat is selected and to provide the respective signals having a floating voltage when the memory mat is unselected, wherein the driving signal driver comprises a driver circuit, the driver circuit comprising:
a signal driver circuit configured to provide a driving signal having the first voltage or the second voltage responsive to a selection signal, and further configured to provide the driving signal having a floating voltage responsive to an active enable signal; and
a control circuit configured to receive a float enable signal and a memory mat activation signal, and further configured to provide an active enable signal to the signal driver responsive to an active float enable signal and inactive memory mat activation signal.

7. The apparatus of claim 6 wherein the signal driver circuit is further configured to provide a second driving signal having the first voltage when the driving signal has the second voltage and to provide the second driving signal having the second voltage when the driving signal has the first voltage.

8. The apparatus of claim 6 wherein the signal driver circuit comprises an output circuit, the output circuit comprising:
a first transistor configured to be provided the first voltage and to provide the first voltage to an output when activated;
a second transistor configured to be provided the second voltage and to provide the second voltage when activated; and
a third transistor coupled between the second transistor and the output and configured to provide the second voltage to the output when activated and to allow the output to float when not activated responsive to the float enable signal.

9. The apparatus of claim 8 wherein the signal driver circuit further comprises a second output circuit configured to provide a complementary driving signal.

10. The apparatus of claim 6 wherein the signal driver circuit is configured to receive first and second control signals, wherein the signal driver circuit is further configured to provide the driving signal having a voltage responsive to a logic level of the selection signal when the first and second control signals are active and to provide the driving signal having a second voltage when the first control signal is inactive.

11. The apparatus of claim 6 , wherein a subword driver of the plurality of subword drivers comprises:
first and second transistors series coupled and coupled to the main word line, the first transistor configured to be provided the driving signal; and
a third transistor coupled to a common node of the first and second transistors.

12. The apparatus of claim 6 , wherein the memory mat includes a plurality of memory cell array regions and wherein the main word line extends across the plurality of memory cell array regions.

13. The apparatus of claim 12 wherein the memory cell array regions of the memory mat are arranged two array regions wide.

14. The apparatus of claim 12 wherein the memory cell array regions of the memory mat are arranged one array region wide.

15. A method, comprising:
driving a word line driver for a selected word line of a selected memory mat of a plurality of memory mats to a first voltage;
driving word line drivers for unselected word lines of the selected memory mat of the plurality of memory mats to a second voltage; and
providing an active enable signal responsive to an active float enable signal and an ina

Assignees

• Micron Technology Inc

Inventors

• Yamanaka Satoshi
• Okahiro Tetsuaki

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title