Display panel and electronic apparatus including the same

US10347187B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10347187-B2
Application numberUS-201816051632-A
CountryUS
Kind codeB2
Filing dateAug 1, 2018
Priority dateJun 17, 2016
Publication dateJul 9, 2019
Grant dateJul 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel including a substrate that includes a display region and a non-display region, the display region including a first and second display region spaced apart from each other, and the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first and second display region; a plurality of first pixels arranged on the first display region; a plurality of second pixels arranged on the second display region; a first and second voltage wiring on the non-display region to transmit a first and second driving voltage to the first and second pixel; and an auxiliary wiring extending in a second direction perpendicular to the first direction, on the intermediate non-display region, the auxiliary wiring crossing between the first and second display region, and being connected to one of the first and second voltage wiring.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a substrate; a display region defined in the substrate, the display region including a first display region and a second display region spaced apart from each other in a first direction; a non-display region defined in the substrate, the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first display region and second display region; a plurality of first pixel circuits on the first display region; a plurality of second pixel circuits on the second display region; a first pad connected to at least one of the first pixel circuits on the edge non-display region; a second pad connected to at least one of the second pixel circuits on the edge non-display region; and a first voltage wiring transmitting a first driving voltage to the first and second pixel circuits, wherein the first voltage wiring includes: a first portion extending in the first direction on a first side of the edge non-display region; a second portion extending in the first direction on a second side of the edge non-display region, the second side being opposite to the first side; and a third portion extending in a second direction, which is perpendicular to the first direction, on the intermediate non-display region. 2. The display panel of claim 1 , further comprising: a first gate driving circuit disposed on the intermediate non-display region and connected to at least one of the first pixel circuits; and a second gate driving circuit disposed on the intermediate non-display region and connected to at least one of the second pixel circuits. 3. The display panel of claim 2 , wherein the third portion of the first voltage wiring is disposed between the first gate driving circuit and the second gate driving circuit. 4. The display panel of claim 2 , further comprising: first gate lines each extending in the first direction on the first display region and each connected to first pixel circuits on an same row among the first pixel circuits; and second gate lines each extending in the first direction on the second display region and each connected to second pixel circuits on an same row among the second pixel circuits, wherein the first gate driving circuit is connected to the first gate lines and drives the first gate lines and the second gate driving circuit is connected to the second gate lines and drives the second gate lines. 5. The display panel of claim 1 , wherein the third portion of the first voltage wiring is integrally formed with to the first and second portions of the first voltage wiring. 6. The display panel of claim 1 , further comprising a second voltage wiring transmitting a second driving voltage to the first and second pixel circuits, wherein the second voltage wiring includes: a first portion disposed between the first pad and the first display region; and a second portion disposed between the second pad and the second display region. 7. The display panel of claim 6 , wherein the second voltage wiring is disposed between the second portion of the first voltage wiring and the first and second display regions. 8. The display panel of claim 6 , further comprising a common electrode entirely covering the first and second display regions and electrically connected to the second voltage wiring. 9. The display panel of claim 8 , further comprising: a plurality of first light-emitting devices arranged on the first display region and electrically connected to the plurality of first pixel circuits, respectively; and a plurality of second light-emitting devices arranged on the second display region and electrically connected to the plurality of first pixel circuits, respectively, wherein each of the first and second light-emitting devices is connected to the common electrode. 10. The display panel of claim 6 , wherein the second driving voltage has a voltage level higher than that of the first driving voltage. 11. The display panel of claim 1 , wherein the third portion of the first voltage wiring includes a first end directly connected to the first portion of the first voltage wiring and a second end directly connected to the second portion of the first voltage wiring. 12. The display panel of claim 1 , wherein the first voltage wiring further includes: a fourth portion extending in the second direction on a third side of the edge non-display region; and a fifth portion extending in the second direction on a fourth side of the edge non-display region, the third side being opposite to the fourth side. 13. The display panel of claim 1 , wherein the first and second pads disposed on the second side of the edge non-display region. 14. An electronic apparatus, comprising: the display panel of claim 1 : a power supply to supply the first driving voltage to the display panel; and a processor to provide image data to the display panel. 15. The electronic apparatus of claim 14 , further comprising: a first optical system in front of the first display region of the display panel; and a second optical system in front of the second display region of the display panel. 16. The electronic apparatus of claim 15 , wherein the electronic apparatus is a head mounted display apparatus mountable on a head or a face. 17. A display panel, comprising: a substrate; a display region defined in the substrate, the display region including a first display region and a second display region spaced apart from each other in a first direction; a non-display region defined in the substrate, the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first display region and second display region; a plurality of first pixel circuits on the first display region; a plurality of second pixel circuits on the second display region; and a first voltage wiring transmitting a first driving voltage to the first and second pixel circuits, wherein the first voltage wiring includes: a first portion extending in the first direction on a first side of the edge non-display region; a second portion extending in the first direction on a second side of the edge non-display region, the second side being opposite to the first side; and a third portion extending in a second direction, which is perpendicular to the first direction, on the intermediate non-display region. 18. The display panel of claim 17 , further comprising: a first gate driving circuit disposed between the first display region and the third portion of the first voltage wiring on the intermediate non-display region and outputs a first scan signal to the first pixel circuits; and a second gate driving circuit disposed between the second display region and the third portion of the first voltage wiring on the intermediate non-display region and outputs a second scan signal to the second pixel circuits. 19. The display panel of claim 17 , wherein the third portion of the first voltage wiring includes a first end directly connected to the first portion of the first voltage wiring and a second end directly connected to the second portion of the first voltage wiring, the second end being opposite to the first end. 20. The display panel of claim 17 , further comprising: a plurality of first pads on the second side of the edge non-display region; and a plurality of second pads on the second side of the edge non-display region, wherein at least one o

Assignees

Inventors

Classifications

  • in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • G09G3/3258Primary

    with pixel circuitry controlling the voltage across the light-emitting element · CPC title

  • Power management, e.g. power saving · CPC title

  • to produce spatial visual effects · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

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What does patent US10347187B2 cover?
A display panel including a substrate that includes a display region and a non-display region, the display region including a first and second display region spaced apart from each other, and the non-display region including an edge non-display region that surrounds the display region and an intermediate non-display region between the first and second display region; a plurality of first pixels…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3258. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).