Image recognition accelerator, terminal device, and image recognition method

Patent metadata

Field	Value
Publication number	US-10346701-B2
Application number	US-201715695681-A
Country	US
Kind code	B2
Filing date	Sep 5, 2017
Priority date	Mar 6, 2015
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

First claim

What is claimed is:

1. An image recognition accelerator of a terminal device for image recognition, comprising:
a dimensionality-reduction processing module, configured to:
receive a dimensionality-reduction parameter γ, and
perform a dimensionality reduction on a first image data to obtain a reduced first image data according to the received dimensionality-reduction parameter γ, wherein the reduced first image data comprises multiple numeric values, and the dimensionality-reduction parameter γ is obtained according to a system power consumption of the terminal device and a first image recognition success rate of the terminal device;

a non-volatile memory (NVM), configured to:
receive a width parameter ω and a first current I, store, in a first storage area of the NVM according to the first current I, ω low-order bits of each numeric value of the reduced first image data, and
store, in a second storage area of the NVM according to a second current I s , (N−ω) high-order bits of each numeric value of the reduced first image data, wherein each numeric value is represented by N bits, the first current I is lower than the second current I s , and the width parameter ω and the first current I are obtained according to the system power consumption of the terminal device and the first image recognition success rate of the terminal device; and

an image matching module, configured to determine whether an image library stored in the NVM comprises image data matching the reduced first image data.

2. The image recognition accelerator according to claim 1 , further comprising:
a parameter adjustment module, configured to:
adjust, according to the first image recognition success rate and the system power consumption of the terminal device, a value of at least one of the following parameters: the dimensionality-reduction parameter, the width parameter, or the first current, wherein the dimensionality-reduction parameter γ, the width parameter ω, and the first current I are obtained based on the adjustment of the value;
send the dimensionality-reduction parameter γ to the dimensionality-reduction processing module; and
send the width parameter ω and the first current I to the NVM.

3. The image recognition accelerator according to claim 2 , wherein the parameter adjustment module is configured to:
separately adjust the value of the dimensionality-reduction parameter, the width parameter, or the first current, to obtain multiple adjusted image recognition success rates and multiple adjusted system power consumptions, wherein each adjusted image recognition success rate corresponds to one adjusted system power consumption;
select a lowest system power consumption from at least one adjusted system power consumption corresponding to at least one adjusted image recognition success rate, wherein an absolute value of a difference between each of the at least one adjusted image recognition success rate and the first image recognition success rate is not greater than a preset threshold; and
select values of the dimensionality-reduction parameter γ, the width parameter ω, and the first current I according to a highest image recognition success rate with the lowest system power consumption;
send the dimensionality-reduction parameter γ to the dimensionality-reduction processing module; and
send the width parameter ω and the first current I to the NVM.

4. The image recognition accelerator according to claim 1 , wherein
the parameter adjustment module is further configured to: if an absolute value of a difference between a calculated image recognition success rate and a second image recognition success rate is greater than a preset threshold, adjust, according to the second image recognition success rate and the system power consumption of the terminal device, a value of at least one of the following parameters: the dimensionality-reduction parameter, the width parameter, or the first current, to obtain an adjusted dimensionality-reduction parameter γ′, an adjusted width parameter ω′, and an adjusted first current I′, wherein the second image recognition success rate is different from the first image recognition success rate;
the dimensionality-reduction processing module is further configured to perform the dimensionality reduction on a second image data to obtain a reduced second image data according to the adjusted dimensionality-reduction parameter γ′;
the non-volatile memory NVM is further configured to: store, in the first storage area of the NVM according to the adjusted first current I′, ω′ low-order bits of each numeric value of the reduced second image data, and store, in the second storage area of the NVM according to the second current I s , (N−ω′) high-order bits of each numeric value of the reduced second image data, wherein I′ is lower than I s ; and
the image matching module is further configured to determine whether the image library stored in the NVM comprises image data matching the reduced second image data.

5. The image recognition accelerator according to claim 4 , further comprising:
a statistics collection module, configured to collect statistics on output of the image matching module within a collection period, wherein the calculated image recognition success rate is based on the collected statistics.

6. The image recognition accelerator according to claim 4 , wherein the parameter adjustment module is configured to:
if an absolute value of a difference between a calculated image recognition success rate and the second image recognition success rate is greater than the preset threshold, separately adjust the value of the dimensionality-reduction parameter, the width parameter, or the first current, to obtain multiple adjusted image recognition success rates and multiple adjusted system power consumptions E, wherein a value of E is proportional to a value of γ((N−ω)*I s 2 +ω*I), and each adjusted image recognition success rate corresponds to one adjusted system power consumption;
select a lowest system power consumption E′ from at least one adjusted system power consumption corresponding to at least one adjusted image recognition success rate, wherein an absolute value of a difference between each of the at least one adjusted image recognition success rate and the second image recognition success rate is not greater than the preset threshold; and
select values of the adjusted dimensionality-reduction parameter γ′, the adjusted width parameter ω′, and the adjusted first current I′ according to a highest image recognition success rate with the lowest power consumption E′;
send the adjusted dimensionality-reduction parameter γ′ to the dimensionality-reduction processing module; and send the adjusted width parameter ω′ and the adjusted first current I′ to the NVM.

7. The image recognition accelerator according to claim 1 , wherein the dimensionality reduction is performed according to the first image data and a binary matrix, wherein the first image data includes a matrix with k rows and m columns, the binary matrix includes a matrix with m rows and n columns, and the reduced first image data includes a matrix with k rows and n columns, wherein k, m, and n are positive integers, a value of m is greater than a value of n, the value of n is determined according to the dimensionality-reduction parameter γ, and γ=n/m.

8. The image recognition accelerator according to claim 7 , wherein the binary matrix comprises a Bernoulli mapping matrix.

9. A terminal device, comprising a central processing unit (CPU) and an image recognition accelerator, wherein
the CPU is configured to send to-be-recognized first image data to the image recognition accelerator; and
the image recognition accelerator is configured to: perform a dimensio

Assignees

• Huawei Tech Co Ltd
• Univ Nanyang Tech

Inventors

• Yu Hao
• Wang Yuhao
• Ni Leibin
• Yang Wei
• Zhao Junfeng
• Xiao Shihai

Classifications

• G06F18/22

  Matching criteria, e.g. proximity measures · CPC title

• G06V10/94 Primary

  Hardware or software architectures specially adapted for image or video understanding · CPC title

• G06K9/00

  Physics · mapped topic

• G06K9/6201

  Physics · mapped topic

• G06K9/00973 Primary

  Physics · mapped topic