Superconducting quantum processor and method of operating same
US-2019019099-A1 · Jan 17, 2019 · US
US10346349B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10346349-B2 |
| Application number | US-201816173846-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 29, 2018 |
| Priority date | Dec 23, 2004 |
| Publication date | Jul 9, 2019 |
| Grant date | Jul 9, 2019 |
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Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
Opening claim text (preview).
We claim: 1. An analog processor, comprising: a plurality of quantum devices; and a plurality of coupling devices, a first coupling device in the first plurality of coupling devices coupling a first quantum device and a second quantum device in the plurality of quantum devices, and a second coupling device in the plurality of coupling devices coupling the first quantum device and a third quantum device in the plurality of quantum devices, wherein the first coupling device in the plurality of coupling devices is one of an rf-SQUID and a dc-SQUID, and the second coupling device in the plurality of coupling devices is a direct galvanic coupling. 2. The analog processor of claim 1 , wherein the first quantum device and the third quantum device in the plurality of quantum devices are ferromagnetically coupled, and, in operation, have a same quantum state. 3. The analog processor of claim 1 , wherein the second coupling device includes: a first section fabricated in a first metal layer of an integrated circuit; and a second section fabricated in a second metal layer of the integrated circuit, the second section electrically coupled to the first section by a via. 4. The analog processor of claim 3 , wherein the plurality of quantum devices are arranged in a lattice, the first and the second quantum devices are nearest neighbors, and the first and the third quantum devices are more distant than next-nearest neighbors. 5. The analog processor of claim 1 , wherein the plurality of quantum devices are arranged in a lattice, the second quantum device is at a Manhattan distance of one from the first quantum device, and the third quantum device is at a Manhattan distance of greater than two from the first quantum device. 6. The analog processor of claim 1 , wherein the plurality of quantum devices are arranged in a lattice, the first and the second quantum devices are nearest neighbors, and the first and the third quantum devices are more distant than next-nearest neighbors. 7. The analog processor of claim 1 , wherein the plurality of quantum devices are arranged in a lattice, the second quantum device is at a Manhattan distance of one from the first quantum device, and the third quantum device is at a Manhattan distance of greater than two from the first quantum device.
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