Signal path isolation for conductive circuit paths and multipurpose interfaces

US10346339B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10346339-B2
Application numberUS-201514920674-A
CountryUS
Kind codeB2
Filing dateOct 22, 2015
Priority dateMar 1, 2013
Publication dateJul 9, 2019
Grant dateJul 9, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A device can be configured to provide isolation between conductive circuit paths and to selectively connect one of the conductive circuit paths to a shared interface. Each conductive circuit path can include driver circuitry designed to transmit signals according to a particular protocol and a corresponding signal speed. The shared interface can be, in one instance, a connector designed for connection to other devices. The other devices can be configured to communicate over the shared interface using one or more of the particular protocols provided using the different circuit paths.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: reducing high-speed loading between conductive signal circuit paths that share a multipurpose signal interface which passes conductively-carried signals received from respective ones of the conductive signal circuit paths to facilitate use of different protocols for communication in each path, wherein the multipurpose signal interface includes gating transistors configured and arranged with a first multiplexer circuit and a second multiplexer circuit; controlling, by generating and using control bits, transmission speeds and signal distortion times over the multipurpose signal interface by selectively using the gating transistors, the first multiplexer circuit and the second multiplexer circuit selectively in order to affect at least one of capacitive and inductive loading on certain signals selected for transmission over the multipurpose signal interface; transmitting different electrical data signals including an electrical data signal, at a signal speed designed for use with a first protocol and on a first conductive signal circuit path, including an electrical data signal, at a signal speed designed for use with a second protocol that is different than the first protocol and that is slower relative to the signal speed designed for use with the first protocol, on a second conductive signal circuit path, and including an electrical data signal, at a speed designed for use with a third protocol that is different than the first and second protocols and that is slower relative to the signal speed designed for use with the first protocol, on a third conductive signal circuit path; transmitting, using the first multiplexer circuit, a signal on a first output conductive signal circuit path by selecting, in response to a first control bit among the control bits, between the second conductive signal circuit path and the third conductive signal circuit path and by electrically isolating the other of the second conductive signal circuit path and the third conductive signal circuit path from the first output conductive signal circuit path; transmitting, using the second multiplexer circuit, a signal on a second output conductive signal circuit path by selecting, in response to a second control bit among the control bits, between the first conductive signal circuit path and the first output conductive signal circuit path; and generating the first and second control bits in response to a selection of one of the first, second and third protocols for use of the multipurpose signal interface, wherein the different protocols are used by different external devices configured to couple to the respective conductive signal circuit paths and being associated with different signal speeds. 2. The method of claim 1 , further including transmitting, using the second multiplexer circuit and in response to the second control bit indicating a selection of the first conductive signal circuit path, a signal on a second output conductive signal circuit path that is a wire-OR of the first conductive signal circuit path and the first output conductive signal circuit path. 3. The method of claim 1 , wherein the first protocol includes one of Serial Peripheral Interface Bus (SPI) with Universal Serial Bus (USB), DisplayPort and Thunderbolt, and the second protocol includes one of Display Data Channel (DDC) and/or Inter-Integrated Circuit (I 2 C). 4. The method of claim 1 , wherein the second protocol includes one of Display Data Channel (DDC) and/or Inter-Integrated Circuit (I 2 C). 5. The method of claim 1 , further including biasing the first output conductive signal circuit path to prevent voltage drift. 6. The method of claim 1 , further including detecting a protocol used by an external device connected to the multipurpose signal interface and wherein the step of generating control bits is responsive to the detection of the protocol used by the connected external device. 7. The method of claim 1 , further including detecting a protocol used by a first external device connected to the multipurpose signal interface and enabling and disabling signal conditioning circuitry in response to the detection of the protocol used by the connected first external device. 8. An apparatus comprising: circuitry configured to reduce high-speed loading between conductive signal circuit paths that share a multipurpose signal interface which passes conductively-carried signals received from respective ones of the conductive signal circuit paths to facilitate the use of different protocols for communication in each path, wherein the multipurpose signal interface includes gating transistors configured and arranged with a first multiplexer circuit and a second multiplexer circuit; circuitry configured to control, by generating and using control bits, transmission speeds and signal distortion times over the multipurpose signal interface by selectively using the gating transistors, the first multiplexer circuit and the second multiplexer circuit selectively to affect at least one of capacitive and inductive loading on certain signals selected for transmission over the multipurpose signal interface; circuitry configured to transmit different electrical data signals including an electrical data signal, at a signal speed designed for use with a first protocol and on a first conductive signal circuit path, including an electrical data signal, at a signal speed designed for use with a second protocol that is different than the first protocol and that is slower relative to the signal speed designed for use with the first protocol, on a second conductive signal circuit path, and including an electrical data signal, at a speed designed for use with a third protocol that is different than the first and second protocols and that is slower relative to the signal speed designed for use with the first protocol, on a third conductive signal circuit path; circuitry configured to transmit, using the first multiplexer circuit, a signal on a first output conductive signal circuit path by selecting, in response to a first control bit among the control bits, between the second conductive signal circuit path and the third conductive signal circuit path and by electrically isolating the other of the second conductive signal circuit path and the third conductive signal circuit path from the first output conductive signal circuit path; circuitry configured to transmit, using the second multiplexer circuit, a signal on a second output conductive signal circuit path by selecting, in response to a second control bit among the control bits, between the first conductive signal circuit path and the first output conductive signal circuit path; and circuitry configured to generate the first and second control bits in response to a selection of one of the first, second and third protocols for use of the multipurpose signal interface, wherein the different protocols are used by different external devices configured to couple to the respective conductive signal circuit paths and being associated with different signal speeds. 9. The apparatus of claim 8 , wherein at least a portion of the circuitry is further configured to detect a protocol used by a device connected to the multipurpose signal interface and enabling and disabling signal conditioning circuitry in response to the detection of the protocol used by the connected device. 10. The apparatus of claim 9 , wherein at least a portion of the circuitry is further configured to bias the first output conductive signal circuit path to prevent voltage drift, and wherein each multiplexer is configured and arranged to enable and disable a single level of transistors to effect the transmission of a signal on the respective

Assignees

Inventors

Classifications

  • Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

  • by balancing the load, e.g. traffic engineering · CPC title

  • in field-effect transistor switches · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10346339B2 cover?
A device can be configured to provide isolation between conductive circuit paths and to selectively connect one of the conductive circuit paths to a shared interface. Each conductive circuit path can include driver circuitry designed to transmit signals according to a particular protocol and a corresponding signal speed. The shared interface can be, in one instance, a connector designed for con…
Who is the assignee on this patent?
Nxp Bv
What technology area does this patent fall under?
Primary CPC classification G06F13/4068. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).