Systems and methods for maintaining the coherency of a store coalescing cache and a load cache

Patent metadata

Field	Value
Publication number	US-10346302-B2
Application number	US-201715654481-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Jul 30, 2012
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

First claim

What is claimed is:

1. A method for maintaining a cache, comprising:
writing an entry from a level one store coalescing cache into a level two cache; and
writing, by the level two cache, the entry into a level one load cache, wherein the writing of the entry into the level two cache and the writing of the entry into the level one load cache maintains coherency of the store coalescing cache and the level one load cache,
wherein, prior to the writing into the level two cache, the level two cache does not include contents of the store coalescing cache such that the entries in the level two cache do not include addresses of entries in the store coalescing cache.

2. The method of claim 1 , wherein the writing of the entry into the level two cache and the writing of the entry into the level one load cache is performed in a single clock cycle.

3. The method of claim 1 , wherein the writing of the entry into the level two cache and the writing of the entry into the level one load cache is executed at a speed of access of the level two cache.

4. The method of claim 1 , wherein the writing of the entry from the level one store coalescing cache into a level two cache is in response to a write-back request.

5. The method of claim 1 , wherein the writing of the entry into the level one load cache is performed with a write port of the level one load cache.

6. The method of claim 5 , wherein the level two cache is to control the write port of the level one load cache.

7. The method of claim 1 , wherein the writing of the entry into the level one load cache updates a stale entry in the level one load cache.

8. The method of claim 1 , wherein an address associated with the entry has a value associated therewith in the level one store coalescing cache that is different from a corresponding value in the level one load cache before the writing of the entry from the level one store coalescing cache into the level two cache.

9. A cache system comprising:
a level one cache comprising:
a store coalescing cache; and
a load cache;

a level two cache comprising:
a cache controller comprising:
a write-back accessing component to access a write-back request to the store coalescing cache; and
a writing component to write an entry into the level two cache and to write the entry into the load cache such that the level two cache directly writes the entry to the load cache on behalf of the store coalescing cache, wherein the writing of the entry into the level two cache and the writing of the entry into the load cache maintain coherency of the store coalescing cache and the load cache,
wherein, prior to the writing into the level two cache, the level two cache does not include contents of the store coalescing cache such that the entries in the level two cache do not include addresses of entries in the store coalescing cache.

10. The cache system of claim 9 , wherein the writing component is to write the entry into the level two cache and into the load cache in response to the write-back request.

11. The cache system of claim 9 , wherein the writing of the entry into the level two cache and the writing of the entry into the load cache is performed in a single clock cycle.

12. The cache system of claim 9 , wherein the writing the entry into the level two cache and the writing the entry into the load cache is executed at a speed of access of the level two cache.

13. The cache system of claim 9 , wherein the writing of the entry into the level two cache and the writing of the entry into the load cache is executed at a pipeline speed of the level two cache.

14. The cache system of claim 9 , wherein the writing of the entry into the load cache is performed with a write port of the load cache.

15. The cache system of claim 14 , wherein the level two cache is to control the write port of the load cache.

16. The cache system of claim 9 , wherein the writing of the entry into the load cache updates a stale entry in the load cache.

17. The cache system of claim 9 , wherein an address associated with the entry has a value associated therewith in the store coalescing cache that is different from a corresponding value in the load cache before the writing of the entry into the level two cache.

18. A processor, comprising:
a cache system, comprising:
a level one cache comprising:
a first cache portion; and
a second cache portion;

a level two cache comprising:
a cache controller comprising:
a write-back accessing component to access a write- back request to the first cache portion; and
a writing component to write an entry into the level two cache and to write the entry into the second cache portion such that the level two cache directly writes the entry to the load cache on behalf of the store coalescing cache, wherein the writing of the entry into the level two cache and the writing of the entry into the second cache portion maintain coherency of the first cache portion and the second cache portion,
wherein, prior to the writing into the level two cache, the level two cache does not include contents of the store coalescing cache such that the entries in the level two cache do not include addresses of entries in the store coalescing cache.

19. The processor of claim 18 , wherein the writing component is to write the entry into the level two cache and to write the entry into the second cache portion in response to the write-back request.

20. The processor of claim 18 , wherein the writing of the entry to the second cache portion is executed at the speed of access of the level two cache.

Assignees

• Intel Corp

Inventors

• Avudaiyappan Karthikeyan
• Abdallah Mohammad

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F2212/1048

  Scalability · CPC title

• G06F12/12

  Replacement control · CPC title