Memory system and method for operating the same

Patent metadata

Field	Value
Publication number	US-10346301-B2
Application number	US-201715653990-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Oct 19, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

First claim

What is claimed is:

1. A method for operating a memory device, comprising:
repairing, in a first soft post-package repair operation, target memory cells of normal memory cells with redundant memory cells, the target memory cells being non-defective memory cells;
writing a secure data in the redundant memory cells;
recovering, in a second soft post-package repair operation, the repairing of the target memory cells with the redundant memory cells so that the secure data written in the redundant memory cells is not accessible;
when the secure data written in the redundant memory cells is requested to be read out, repairing, in a third soft post-package repair operation, the target memory cells of the normal memory cells with the redundant memory cells so that the secure data written in the redundant memory cells is accessible; and
reading the secure data from the redundant memory cells.

2. The method of claim 1 , wherein the repairing of the target memory cells of the normal memory cells with the redundant memory cells includes:
entering the first soft post-package repair operation mode;
replacing the target memory cells with the redundant memory cells; and
exiting the first soft post-package repair operation mode.

3. The method of claim 1 , wherein the writing of the secure data in the redundant memory cells includes:
receiving a write command and an address designating the target memory cells from a memory controller; and
writing the secure data in the redundant memory cells based on the write command and the address.

4. The method of claim 1 , wherein the recovering of the repairing of the target memory cells with the redundant memory cells includes:
entering the second soft post-package repair operation mode;
canceling the repairing of the target memory cells with the redundant memory cells; and
exiting the second soft post-package repair operation mode.

5. The method of claim 1 , wherein the repairing of the target memory cells of the normal memory cells with the redundant memory cells includes:
entering the third soft post-package repair operation mode;
replacing the target memory cells with the redundant memory cells; and
exiting the third soft post-package repair operation mode.

6. The method of claim 1 , wherein the reading of the secure data from the redundant memory cells includes:
receiving a read command and an address designating the target memory cells from a memory controller; and
reading the secure data from the redundant memory cells based on the read command and the address.

7. A memory system comprising:
a memory device; and
a memory controller suitable for controlling the memory device, and
the memory device comprises:
a plurality of normal memory cells;
a plurality of redundant memory cells; and
a soft repair circuit suitable for repairing the normal memory cells with the redundant memory cells,

wherein, the memory controller is configured to:
control the soft repair circuit to repair target memory cells of the normal memory cells with the redundant memory cells, the target memory cells being non-defective memory cells,
control the memory device to write a secure data in the redundant memory cells, and control the soft repair circuit to recover the repairing of the target memory cells with the redundant memory cells so that the secure data written in the redundant memory cells is not accessible,
control, when the secure data written in the redundant memory cells is requested to be read out, the soft repair circuit to repair the target memory cells of the normal memory cells with the redundant memory cells so that the secure data written in the redundant memory cells is accessible, and then control the memory device to read the secure data from the redundant memory cells.

8. The memory system of claim 7 , wherein the soft repair circuit repairs the target memory cells with the redundant memory cells, as the memory device enters a first soft post-package repair operation mode, and the soft repair circuit replaces the target memory cells with the redundant memory cells, and the memory device exits the first soft post-package repair operation mode.

9. The memory system of claim 7 , wherein the memory device writes the secure data in the redundant memory cells based on addresses designating the target memory cells and a write command provided to the memory device from the memory controller.

10. The memory system of claim 7 , wherein the soft repair circuit recovers the repairing of the target memory cells with the redundant memory cells, as the memory device enters a second soft post-package repair operation mode, and the soft repair circuit cancels the repairing of the target memory cells with the redundant memory cells, and the memory device exists the second soft post-package repair operation mode.

11. The memory system of claim 7 , wherein the soft repair circuit repairs the target memory cells with the redundant memory cells, as the memory device enters a third soft post-package repair operation mode, and the soft repair circuit replaces the target memory cells with the redundant memory cells, and the memory device exits the third soft post-package repair operation mode.

12. The memory system of claim 7 , wherein the memory device read the secure data from the redundant memory cells based on addresses designating the target memory cells and a read command provided to the memory device from the memory controller.

Assignees

• Sk Hynix Inc

Inventors

• JO Sang-Gu
• Kim Yong-Ju

Classifications

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G11C11/407

  for memory cells of the field-effect type · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title

• G11C11/34

  using semiconductor devices · CPC title

• G06F13/1647 Primary

  with interleaved bank access · CPC title