Fabric resiliency support for atomic writes of many store operations to remote nodes

Patent metadata

Field	Value
Publication number	US-10346091-B2
Application number	US-201615324107-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
non-volatile memory to store data corresponding to a plurality of write operations; and
a first node to comprise logic, at least a portion of which is in hardware, to perform one or more operations, in response to the plurality of write operations, to cause storage of the data at a second node atomically,
wherein the logic is to atomically bind the plurality of write operations to a transaction in response to a first instruction that indicates an identifier of the transaction and an identifier of the second node, and to release the transaction in response to a second instruction that indicates the identifier of the transaction, wherein the data is written to the non-volatile memory in response to release of the transaction.

2. The apparatus of claim 1 , wherein the second node is to be coupled to one or more non-volatile memory nodes.

3. The apparatus of claim 1 , wherein each of the first node or the second node is to comprise one or more sockets.

4. The apparatus of claim 3 , wherein at least one of the one or more sockets of the first node or the second node is to be coupled to a volatile memory or a high bandwidth memory.

5. The apparatus of claim 1 , wherein the first node is in a first domain and the second node is in a second domain.

6. The apparatus of claim 5 , wherein the first domain and the second domain are to form a Non-Uniform Memory Access (NUMA) system.

7. The apparatus of claim 1 , wherein the first node is to be coupled to the second node via a network link.

8. The apparatus of claim 7 , wherein the network link is to communicate the data via a switch.

9. The apparatus of claim 8 , wherein the switch is to communicate with the first node or the second node via a Host Fabric Interface (HFI).

10. The apparatus of claim 8 , wherein the switch is to communicate with the first node or the second node via a Unified Path Interconnect (UPI) tunnel or QuickPath Interconnect (QPI) tunnel.

11. The apparatus of claim 1 , wherein the non-volatile memory is to be coupled to a two-level system main memory to at least temporarily store a portion of the data.

12. The apparatus of claim 1 , wherein the non-volatile memory is to comprise one or more of: nanowire memory, Ferro-electric Transistor Random Access Memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM), flash memory, Spin Torque Transfer Random Access Memory (STTRAM), Resistive Random Access Memory, byte addressable 3-Dimensional Cross Point Memory, PCM (Phase Change Memory), and volatile memory backed by a power reserve to retain data during power failure or power disruption.

13. The apparatus of claim 1 , comprising one or more of: at least one processor, having one or more processor cores, communicatively coupled to the non-volatile memory, a battery communicatively coupled to the apparatus, or a network interface communicatively coupled to the apparatus.

14. A method comprising:
storing data corresponding to a plurality of write operations in non-volatile memory; and
performing, at a first node, one or more operations, in response to the plurality of write operations, to cause storage of the data at a second node atomically,
wherein the one or more operations atomically bind the plurality of write operations to a transaction in response to a first instruction that indicates an identifier of the transaction and an identifier of the second node, and to release the transaction in response to a second instruction that indicates the identifier of the transaction, wherein the data is written to the non-volatile memory in response to release of the transaction.

15. The method of claim 14 , further comprising coupling the second node to one or more non-volatile memory nodes.

16. The method of claim 14 , further comprising coupling the first node and the second node via a network link.

17. The method of claim 14 , further comprising a network link coupling the first node and the second node via a switch.

Assignees

• Intel Corp

Inventors

• Guim Bernat Francesc
• Willhalm Thomas
• Kumar Karthik
• Dimitrov Martin P
• Ramanujan Raj K

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title