Combined analog architecture and functionality in a mixed-signal array

Patent metadata

Field	Value
Publication number	US-10345377-B2
Application number	US-201815944244-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	May 5, 2009
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

First claim

What is claimed is:

1. A circuit comprising:
a plurality of programmable digital blocks configured according to at least one configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks;
a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to the at least one configuration register upon receipt of the DMA request.

2. The circuit of claim 1 , further comprising:
a digital system interconnect (DSI) coupled to the plurality of programmable digital blocks and the DMA controller.

3. The circuit of claim 1 , further comprising:
a peripheral HUB (PHUB) coupled to the plurality of programmable digital blocks and the DMA controller.

4. The circuit of claim 1 , wherein the plurality of programmable digital blocks are programmable logic arrays.

5. The circuit of claim 1 , wherein the at least one programmable digital block is coupled to an interrupt controller for generating an interrupt signal.

6. The circuit of claim 1 , wherein the program information written to the at least one configuration register is for dynamically reconfiguring the plurality of programmable digital blocks in response to the DMA request.

7. The circuit of claim 6 , wherein the dynamically reconfiguring the plurality of programmable digital blocks in response to the DMA request is performed without central processing unit (CPU) control.

8. A method comprising:
receiving a direct memory access (DMA) request from at least one of a plurality of programmable digital blocks in response to an event detected by the plurality of programmable digital blocks;
retrieving configuration information using a DMA controller from a memory in response to the DMA request; and
writing the program information using the DMA controller from the memory to at least one configuration register.

9. The method of claim 8 , further comprising:
reconfiguring a programmable circuit in response to the program information written to the at least one configuration register, wherein the reconfiguration is performed without action by a central processing unit (CPU).

10. The method of claim 8 , wherein the DMA request is received through a digital system interconnect (DSI) coupled to the at least one of the plurality of programmable digital blocks.

11. The method of claim 8 , further comprising:
generating an interrupt with an interrupt controller coupled to the at least one of the plurality of programmable digital blocks, the interrupt provided to a central processing unit (CPU).

12. A system comprising:
a central processing unit (CPU);
a memory;
a programmable circuit comprising a plurality of programmable digital blocks configured according to at least one configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks;
a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to the at least one configuration register upon receipt of the DMA request.

13. The system of claim 12 , further comprising:
a digital system interconnect (DSI) coupled to the plurality of programmable digital blocks and the DMA controller.

14. The system of claim 12 , further comprising:
a peripheral HUB (PHUB) coupled to the CPU, the plurality of programmable digital blocks, and the DMA controller.

15. The system of claim 12 , wherein the plurality of programmable digital blocks are programmable logic arrays.

16. The system of claim 12 , wherein the at least one programmable digital block is coupled to an interrupt controller for generating an interrupt signal.

17. The system of claim 16 , wherein the interrupt signal is provided to the CPU.

18. The system of claim 12 , wherein the program information written to the at least one configuration register is for dynamically reconfiguring the programmable circuit in response to the DMA request.

19. The system of claim 18 , wherein the dynamically reconfiguring the programmable circuit in response to the DMA request is performed without central processing unit (CPU) action.

20. The system of claim 12 , wherein the DMA controller is coupled to an interrupt controller for providing interrupt signals to the CPU.

Assignees

• Cypress Semiconductor Corp

Inventors

• Kutz Harold M
• Williams Timothy John
• Sullam Bert S
• Snyder Warren S
• Shutt James H
• Byrkett Bruce E
• Mar Monte
• Thiagarajan Eashwar
• Kohagen Nathan Wayne
• Wright David G
• Hastings Mark E
• Seguine Dennis R

Classifications

• H03K19/173

  using elementary logic circuits as components · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title