Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method

US10345348B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10345348-B2
Application numberUS-201514838125-A
CountryUS
Kind codeB2
Filing dateAug 27, 2015
Priority dateNov 4, 2014
Publication dateJul 9, 2019
Grant dateJul 9, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a first logic level when the timer circuit is reset via a reset signal. The timer circuit determines the time elapsed since the last reset and tests whether the time elapsed exceeds a given timeout value. If the time elapsed exceeds the given timeout value, the timer circuit sets the discharge enable signal to a second logic level. A dynamic threshold generator circuit varies the threshold of the comparator circuit as a function of the sensor signal.

First claim

Opening claim text (preview).

The invention claimed is: 1. A detection circuit, comprising: a sensor circuit configured to be coupled to an X capacitor, said sensor circuit configured to generate a sensor signal indicative of a voltage at said X capacitor; a window comparator configured to generate a comparison signal indicating whether said sensor signal is between a lower threshold value and an upper threshold value; a timer circuit configured to: set a discharge enable signal to a first logic level in response to said timer circuit being reset via a reset signal; and determine a time elapsed since said timer circuit has been reset via the reset signal; determine whether said time elapsed exceeds a given timeout value; and if said time elapsed exceeds said given timeout value, set said discharge enable signal to a second logic level to cause the active discharge circuit to discharge the X capacitor; an elaboration circuit configured to generate said reset signal for said timer circuit as a function of said comparison signal, the elaboration circuit configured to: detect whether said comparison signal includes both a leading and a falling edge; and in the case where said comparison signal includes both said leading edge and said falling edge, determine a time elapsed between said leading edge and said falling edge; detect whether said time elapsed between said leading edge and said falling edge is smaller than a given time threshold value; and reset said timer circuit via said reset signal in response to detecting that said time elapsed between said leading and said falling edge is smaller than said given time threshold value; and to generate, based on the comparison signal from said window comparator, first and second control signals indicating whether the sensor signal is increasing or decreasing; and a dynamic threshold generator circuit configured to generate said lower and upper threshold values of said window comparator based on the sensor signal, and said dynamic threshold generator circuit further configured to vary in a feed-back manner said lower and upper threshold values of said window comparator as a function of said first and second control signals from said elaboration circuit. 2. The detection circuit of claim 1 , wherein said elaboration circuit is configured to: detect an edge of said comparison signal; and reset said timer circuit via said reset signal in response to detecting the edge of said comparison signal. 3. The detection circuit of claim 1 , wherein said dynamic threshold generator circuit is configured to vary in a feed-forward manner said lower and upper threshold values of said window comparator as a function of said sensor signal. 4. The detection circuit of claim 3 , wherein said dynamic threshold generator circuit comprises: a peak detector circuit configured to determine the upper threshold value indicative of a peak value of said sensor signal; and a threshold generator circuit configured to determine the lower threshold value as a function of said upper threshold value. 5. The detection circuit of claim 1 , wherein said window comparator comprises: a first comparator configured to generate a first comparison signal indicating whether said sensor signal is greater than the lower threshold value; and a second comparator configured to generate a second comparison signal indicating whether said sensor signal is greater than the upper threshold value. 6. The detection circuit of claim 5 , wherein said elaboration circuit is further configured to: generate, based on said first and said second comparison signals from the window comparator, the first control signal indicating whether said sensor signal is greater than both of said upper and lower threshold values; generate, based on said first and said second comparison signals from the window comparator, the second control signal indicating whether said sensor signal is smaller than both of said upper and lower threshold values; and reset said timer circuit via said reset signal in response to said first and said second comparison signals indicating that said sensor signal is greater than both of said first and second threshold values. 7. The detection circuit of claim 6 , wherein said dynamic threshold generator circuit is further configured to determine, based on the first and second control signals, whether said first and said second comparison signals indicate that said sensor signal is greater than both of said upper and lower threshold values, smaller than both of said upper and lower threshold values, or between said upper and lower threshold values, and wherein the dynamic threshold generator circuit is further configured, in response to said first and second control signals indicating that said sensor signal is greater than both of said upper and lower threshold values, to increase the lower threshold value to a new value that is greater than a current value of the upper threshold value, and wherein the dynamic threshold generator circuit is further configured, in response to said first and second control signals indicating that said sensor signal is smaller than both of said upper and lower threshold values, to decrease the upper threshold value to a value that is smaller than a current value of the lower threshold value. 8. An active discharge circuit, comprising: a detection circuit configured to generate a discharge enable signal signaling whether an AC oscillation is applied to an X capacitor of a device, wherein said detection circuit comprises: a sensor circuit for connection to said X capacitor, said sensor circuit configured to generate a sensor signal indicative of the voltage at said X capacitor; a window comparator circuit configured to generate at least one comparison signal by comparing said sensor signal with a high threshold and a low threshold, the window comparator circuit including: a first comparator configured to generate a first comparison signal indicating whether said sensor signal is greater than a first threshold value; and a second comparator configured to generate a second comparison signal indicating whether said sensor signal is greater than a second threshold value; a timer circuit configured to: set said discharge enable signal to a first logic level responsive to said timer circuit being reset via a reset signal; determine the time elapsed since said timer circuit has been reset via a reset signal; test whether said time elapsed exceeds a given timeout value; and in case said time elapsed exceeds said given timeout value, set said discharge enable signal to a second logic level; an elaboration circuit configured to generate said reset signal for said timer circuit and to generate a first control signal and a second control signal as a function of said first and second comparison signals; and a dynamic threshold generator circuit configured to vary said high and low threshold of said comparator circuit in response to said first and second control signals, the dynamic threshold generator circuit further configured to: determine which of said first and second threshold values is greater; determine whether said first and said second comparison signals indicate that said sensor signal is greater than both of said first and second threshold values; determine whether said first and second comparison signals indicate that said sensor signal is smaller than both of said first and second threshold values; where said first and said second comparison signals indicate that said sensor signal is greater than both of said first and second threshold values, increase the smaller one of said first or said second threshold values; and where said first and said second comparison signals indicate that said sensor signal is smaller tha

Assignees

Inventors

Classifications

  • H02J7/92Primary

    with prioritisation of loads or sources · CPC title

  • using capacitors as storage or buffering devices · CPC title

  • Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title

  • Electricity · mapped topic

  • Logic probes, i.e. circuits indicating logic state (high, low, O); (modifications of electronic switches or gates for indicating state of switch H03K17/18) · CPC title

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What does patent US10345348B2 cover?
An active discharge circuit discharges an X capacitor and includes a sensor circuit that generates a sensor signal indicative of an AC voltage at the X capacitor. A processing unit generates a reset signal as a function of a comparison signal. A comparator circuit generates the comparison signal by comparing the sensor signal with a threshold. A timer circuit sets a discharge enable signal to a…
Who is the assignee on this patent?
St Microelectronics Srl
What technology area does this patent fall under?
Primary CPC classification H02J7/92. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 09 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).