Semiconductor device

Patent metadata

Field	Value
Publication number	US-10342118-B2
Application number	US-201414779961-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Mar 26, 2013
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.

First claim

What is claimed is:

1. A semiconductor device comprising:
a wiring substrate;
a first semiconductor chip installed on one surface of the wiring substrate, the first semiconductor chip having a first edge and a second edge opposite to the first edge;
a second semiconductor chip stacked on the first semiconductor chip so that the second semiconductor chip crosses over the first edge and the second edge of the first semiconductor chip and a portion of a surface of the first semiconductor chip is exposed, wherein the second semiconductor chip is the top most semiconductor chip in the package:
a warp regulating member disposed directly on the exposed portion of the surface, wherein the warp regulating member comprises a first edge that aligns with the first edge of the first semiconductor chip and a second edge that aligns with the second edge of the first semiconductor chip and the warp regulating member covers a majority of the exposed portion of the surface: and
a sealing body formed on the wiring substrate to cover the first semiconductor chip, the second semiconductor chip, and the warp regulating member;
wherein the warp regulating member is a highly-resilient body having a modulus of elasticity higher than that of the sealing body.

2. The semiconductor device as claimed in claim 1 , wherein the warp regulating member is a silicon substrate.

3. The semiconductor device as claimed in claim 1 , wherein the first and second semiconductor chips have a rectangular planar shape and have a long edge and a short edge, and the second semiconductor chip is stacked on the first semiconductor chip so that the long edge of the second semiconductor chip faces the short edge of the first semiconductor chip.

4. The semiconductor device as claimed in claim 1 , further comprising external terminals disposed on another surface of the wiring substrate and electrically connected to the first semiconductor chip.

5. The semiconductor device as claimed in claim 1 , wherein the thickness of the warp regulating member is substantially the same as the thickness of the second semiconductor chip.

6. The semiconductor device as claimed in claim 3 , wherein the second semiconductor chip is cross-stacked in a state rotated relative to the first semiconductor chip so that the planar arrangements of the first semiconductor chip and the second semiconductor chip intersect.

7. The semiconductor device as claimed in claim 3 , wherein the first semiconductor chip has electrode pads disposed along the short edge and electrically connected to the wiring substrate, and the second semiconductor chip is disposed adjacent to the electrode pads.

8. The semiconductor device as claimed in claim 3 , wherein the thickness of the second semiconductor chip is greater than the thickness of the first semiconductor chip.

9. The semiconductor device as claimed in claim 4 , wherein the external terminals are solder balls.

10. The semiconductor device as claimed in claim 7 , further comprising wires electrically connecting the electrode pads to the wiring substrate, wherein the warp regulating member is disposed to cover the electrode pads.

Assignees

• Ps4 Luxco Sarl
• Longitude Licensing Ltd

Inventors

• Usami Sensho

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/073

  of die-attach connectors · CPC title