Ultra low power sensing platform with multimodal radios

Patent metadata

Field	Value
Publication number	US-10340972-B2
Application number	US-201715670386-A
Country	US
Kind code	B2
Filing date	Aug 7, 2017
Priority date	Aug 30, 2012
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a system on chip (SoC) having a first memory circuit portion and a second memory circuit portion, the first memory circuit portion configured to operate at a subthreshold voltage that establishes subthreshold operation of one or more field effect transistors associated with the first memory circuit portion, the subthreshold operation including conduction of current by the one or more field effect transistors, the second memory circuit portion configured to operate at a superthreshold voltage,
the SoC configured to access the second memory circuit portion in response to at least one of (1) signals being sent from the SoC, or (2) signals being received at the SoC.

2. The apparatus of claim 1 , wherein:
the first memory circuit portion is configured to operate at the subthreshold voltage and not at a superthreshold voltage;
the second memory circuit portion is configured to operate at the superthreshold voltage and not at a subthreshold voltage.

3. The apparatus of claim 1 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a first operational mode and a second operational mode,
the memory circuit configured to operate the first memory circuit portion in response to the memory circuit being in the first operational mode, the memory circuit configured to operate the second memory circuit portion in response to the memory circuit being in the second operational mode.

4. The apparatus of claim 1 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a first operational mode and a second operational mode,
the memory circuit configured to operate the first memory circuit portion and not the second memory circuit portion in response to the memory circuit being in the first operational mode, the memory circuit configured to operate the second memory circuit portion and not the first memory circuit portion in response to the memory circuit being in the second operational mode.

5. The apparatus of claim 1 , wherein the subthreshold operation of the one or more field effect transistors comprises one of (1) operating each of the one or more field effect transistors in a weak-inversion mode, (2) operating each of the one or more field effect transistors such that transconductance is at a relative or absolute maximum, or (3) operating each of the one or more field effect transistors such that transconductance is primarily dependent on a threshold voltage and a drain current.

6. The apparatus of claim 1 , wherein:
the SoC includes a wireless communications circuit configured to receive information and to transfer at least a portion of the received information to the first memory circuit portion and/or the second memory circuit portion without use of a digital processor circuit.

7. The apparatus of claim 1 , wherein the SoC is configured to access the first memory circuit portion and not the second memory circuit portion during an execution of a local function within the SoC.

8. The apparatus of claim 1 , wherein the SoC is configured to access the second memory circuit portion and not the first memory circuit portion during an interaction with a component that is external to the SoC.

9. The apparatus of claim 1 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a subthreshold operational mode and a superthreshold operational mode,
the memory circuit configured to switch between operating in the subthreshold operational mode and operating in the superthreshold operational mode in response to the SoC executing a local function within the SoC and the SoC interacting with a component that is external to the SoC, respectively.

10. The apparatus of claim 1 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a subthreshold operational mode and a superthreshold operational mode,
the SoC further comprising:
a power management circuit configured to select an operational mode from a plurality of operational modes based on at least one of (1) an amount of energy incoming to the SoC, (2) an amount of stored energy associated with the SoC, or (3) a rate of power consumption by the SoC, the plurality of operational modes including the subthreshold operational mode and the superthreshold operational mode.

11. A method, comprising:
operating a first memory circuit portion of a system on chip (SoC) at a subthreshold voltage that establishes subthreshold operation of one or more field effect transistors associated with the first memory circuit portion, the subthreshold operation including conduction of current by the one or more field effect transistors;
operating a second memory circuit portion of the SoC at a superthreshold voltage; and
accessing, by the SoC, the second memory circuit portion in response to at least one of (1) signals being sent from the SoC, or (2) signals being received at the SoC.

12. The method of claim 11 , wherein:
operating the first memory circuit portion at the subthreshold voltage includes operating the first memory circuit portion at the subthreshold voltage and not at a superthreshold voltage;
operating the second memory circuit portion at the superthreshold voltage includes operating the second memory circuit portion at the superthreshold voltage and not at a subthreshold voltage.

13. The method of claim 11 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a first operational mode and a second operational mode,
the method further comprising:
operating the first memory circuit portion in response to the memory circuit being in the first operational mode; and
operating the second memory circuit portion in response to the memory circuit being in the second operational mode.

14. The method of claim 11 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a first operational mode and a second operational mode,
the method further comprising:
operating the first memory circuit portion and not the second memory circuit portion in response to the memory circuit being in the first operational mode,
operating the second memory circuit portion and not the first memory circuit portion in response to the memory circuit being in the second operational mode.

15. The method of claim 11 , wherein:
the SoC includes a wireless communications circuit, the method further comprising:
receiving information at the wireless communications circuit and transferring at least a portion of the received information to the first memory circuit portion and/or the second memory circuit portion without use of a digital processor circuit.

16. The method of claim 11 , further comprising accessing, by the SoC, the first memory circuit portion and not the second memory circuit portion during an execution of a local function within the SoC.

17. The method of claim 11 , wherein accessing the second memory circuit portion includes accessing the second memory circuit portion and not the first memory circuit portion during an interaction with a component that is external to the SoC.

18. The method of claim 11 , wherein:
the first memory circuit portion and the second memory circuit portion collectively define a memory circuit having a subthreshold operational mode and a superthresho

Assignees

• Univ Virginia Patent Foundation
• Univ Michigan Regents

Inventors

• Calhoun Benton H
• Shakhsheer Yousef
• Zhang Yanqing
• Klinefelter Alicia
• Wentzloff David D
• Roberts Nathan E
• Oh Seunghyun

Classifications

• H04B1/1607 Primary

  Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46) · CPC title

• H04W4/70

  Services for machine-to-machine communication [M2M] or machine type communication [MTC] · CPC title

• H04B1/406 Primary

  with more than one transmission mode, e.g. analog and digital modes · CPC title

• Y02D70/40

  Cross-Sectional Technologies · mapped topic

• Y02D70/00

  Cross-Sectional Technologies · mapped topic