Fast settling sawtooth ramp generation in a phase-locked loop

Patent metadata

Field	Value
Publication number	US-10340926-B2
Application number	US-201615284190-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Oct 3, 2016
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

First claim

What is claimed is:

1. A phase-locked loop comprising:
an input configured to receive a frequency command word, wherein the frequency command word is an input sawtooth ramp signal;
a loop filter configured to provide a sawtooth ramp signal, wherein the sawtooth ramp signal is periodic and based on the frequency command word, wherein the sawtooth ramp signal has a settling time associated with a transition from a first ramping portion of a first period of the sawtooth ramp signal to a second ramping portion of a second period of the sawtooth ramp signal, and wherein the settling time is less than 1 microsecond; and
an oscillator coupled to the loop filter, the oscillator configured to generate an oscillating signal based on the sawtooth ramp signal.

2. The phase-locked loop of claim 1 , wherein the oscillator is a digitally controlled oscillator and the sawtooth ramp signal represents an oscillator tuning word.

3. The phase-locked loop of claim 1 , further comprising a time-to-digital converter coupled in a feedback path between an output of the oscillator and an input of the loop filter.

4. The phase-locked loop of claim 1 , wherein the phase-locked loop is a type II phase-locked loop.

5. The phase-locked loop of claim 1 , wherein the loop filter comprises a proportional path and a sampling circuit configured to sample a value from the proportional path, and the sawtooth ramp signal is based on an output of the proportional path and an output of the sampling circuit.

6. The phase-locked loop of claim 5 , wherein the loop filter further comprises an integral path configured to reset responsive to a signal indicating a new chirp of the sawtooth ramp signal, and wherein the sawtooth ramp signal is based on an output of the integral path.

7. The phase-locked loop of claim 6 , wherein the loop filter further comprises another proportional path that is inactive after the phase-locked loop is locked.

8. A radar device comprising the phase-locked loop of claim 1 .

9. A phase-locked loop comprising:
a loop filter comprising a proportional path and a sampling circuit configured to sample a value from the proportional path, wherein the loop filter is configured to provide a sawtooth ramp signal based on an output of the sampling circuit and an output of the proportional path, wherein the sawtooth ramp signal is periodic; and
an oscillator coupled to the loop filter, the oscillator configured to generate an oscillating signal based on the sawtooth ramp signal.

10. The phase-locked loop of claim 9 , wherein the loop filter is configured to bring the sawtooth ramp signal to an initial value in association with an end of a chirp to thereby reduce settling time of the sawtooth ramp signal.

11. The phase-locked loop of claim 9 , wherein the sampling circuit is configured to sample the value from the proportional path responsive to a signal indicating a new chirp of the sawtooth ramp signal.

12. The phase-locked loop of claim 9 , wherein the loop filter further comprises an integral path including an accumulator configured to reset responsive a signal indicating a new chirp of the sawtooth ramp.

13. The phase-locked loop of claim 9 , wherein the loop filter comprises a summer configured to subtract the output of the sampling circuit from a value that includes the output of the proportional path to generate the sawtooth ramp signal.

14. The phase-locked loop of claim 9 , wherein the sawtooth ramp signal has a settling time of less than 100 cycles of a reference clock signal provided to the phase-locked loop.

15. The phase-locked loop of claim 9 , wherein the loop filter further comprises another proportional path configured to be active during an acquisition mode of the phase-locked loop.

16. The phase-locked loop of claim 9 , wherein the oscillator comprises a digitally controlled oscillator, wherein the sawtooth ramp signal is an output tuning word for the digitally controlled oscillator.

17. A method of generating a sawtooth ramp signal in a phase-locked loop, the method comprising:
sampling a signal from a loop filter of the phase-locked loop; and
adjusting an output of the loop filter based on a value from said sampling such that the output of the loop filter is the sawtooth ramp signal with a reduced settling time, wherein the sawtooth ramp signal is a periodic signal.

18. The method of claim 17 , further comprising resetting an accumulator of the loop filter responsive to a chirp start signal indicating a start of a chirp of the sawtooth ramp signal, wherein said sampling is performed with a sampling circuit that comprises a digital memory element.

19. The method of claim 17 , wherein said adjusting brings the output of the loop filter to an initial value in association with an end of a chirp.

20. The method of claim 17 , wherein the sawtooth ramp signal has a settling time of less than 1 microsecond.

Assignees

• Analog Devices Global

Inventors

• Chillara Vamshi Krishna
• Dalton Declan M
• Dato Pablo Cruz

Classifications

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03K3/80

  Generating trains of sinusoidal oscillations (by keying or interruption of sinusoidal oscillations H03C; for transmission of digital information H04L) · CPC title

• H03L7/104

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title

• H03K4/90

  Linearisation of ramp (modifying slopes of pulses H03K6/04; scanning distortion correction for television receivers H04N3/23); Synchronisation of pulses · CPC title