ESD protection circuit and method with high immunity to hot plug insertion and other transient events

Patent metadata

Field	Value
Publication number	US-10340687-B2
Application number	US-201615062350-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Mar 7, 2016
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Disclosed examples include an ESD protection circuit to protect an IC pad with high immunity against hot-plug surges, switching noise or other transient voltage conditions on the protected pad. The ESD protection circuit includes a clamp transistor and a trigger circuit responsive to rises in the protected pad voltage at or above a first slew rate to turn on the clamp transistor, as well as a second circuit coupled between the control terminal of the clamp transistor and a voltage supply node. The second circuit responds to rises in a voltage of the clamp transistor control terminal at a second, lower slew rate to reduce the voltage of the first control node to at least partially turn the clamp transistor off to reduce leakage current flow through the clamp transistor during transient voltage conditions on the protected pad.

First claim

The following is claimed:

1. An electrostatic discharge (ESD) protection circuit, comprising:
a first transistor, including a first drain terminal coupled with a protected pad, a first source terminal coupled with a voltage supply node, and a first control terminal coupled to a first control node;
a trigger circuit configured to turn on the first transistor to conduct a current from the protected pad to the voltage supply node in response to a first voltage rise in the protected pad at or above a first slew rate; and
a second circuit coupled between the first control node and the voltage supply node, the second circuit configured to reduce the voltage of the first control node in response to a second voltage rise of the first control node at a second slew rate below the first slew rate, the reduced voltage of the first control node partially reducing the current flow through the first transistor, the second circuit comprising:
a low pass filter circuit to provide a rising filter output signal at a first filter node responsive to the rises in the voltage of the first control node, the low pass filter circuit including a first filter resistor connected between the first control node and the first filter node, and a first filter capacitor connected between the first filter node and the voltage supply node, a filter time constant associated with the first filter resistor and the first filter capacitor of the low pass filter circuit is between 100 ns and 2 μs.

2. The ESD protection circuit of claim 1 , wherein the second circuit includes:
a second transistor, including a second drain terminal coupled with the first control node, a second source terminal coupled with the voltage supply node, and a second control terminal coupled with the first filter node to provide the rising filter output signal for turning on the second transistor.

3. The ESD protection circuit of claim 2 , wherein the second circuit includes an RC circuit including a second resistor and a second capacitor to control a pull down strength of the second circuit, the second resistor connected between the first control node and the second drain terminal of the second transistor, and the second capacitor coupled between the first control node and the voltage supply node.

4. The ESD protection circuit of claim 2 , wherein a filter time constant associated with the first filter resistor and the first filter capacitor of the low pass filter circuit corresponds to the second slew rate.

5. The ESD protection circuit of claim 2 , wherein the trigger circuit includes a first capacitor and a first resistor to control a sensitivity of the trigger circuit, and wherein a trigger circuit time constant associated with the first capacitor and the first resistor corresponds to the first slew rate.

6. The ESD protection circuit of claim 2 , wherein the trigger circuit includes a first capacitor and a first resistor to control a sensitivity of the trigger circuit, and wherein a trigger circuit time constant associated with the first capacitor and the first resistor is 100 ns or less.

7. The ESD protection circuit of claim 6 , wherein the trigger circuit time constant associated with the first capacitor and the first resistor is 50 ns or less.

8. The ESD protection circuit of claim 2 , wherein the trigger circuit includes:
a first trigger circuit transistor connected between the protected pad and the first control node;
a second trigger circuit transistor connected between the first control node and the voltage supply node;
a first capacitor connected between the protected pad and a control terminal of the first trigger circuit transistor;
a first resistor connected between the control terminal of the first trigger circuit transistor and the voltage supply node;
a second resistor connected between the first control node and the voltage supply node; and
a third trigger circuit transistor connected between the control terminal of the first trigger circuit transistor and the voltage supply node;
wherein control terminals of the second and third trigger circuit transistors are connected to a second voltage supply node.

9. The ESD protection circuit of claim 8 , wherein the trigger circuit includes a first capacitor and a first resistor to control a sensitivity of the trigger circuit, and wherein a trigger circuit time constant associated with the first capacitor and the first resistor corresponds to the first slew rate.

10. The ESD protection circuit of claim 8 , wherein the trigger circuit includes a first capacitor and a first resistor to control a sensitivity of the trigger circuit, and wherein a trigger circuit time constant associated with the first capacitor and the first resistor is 100 ns or less.

11. The ESD protection circuit of claim 10 , wherein the trigger circuit time constant associated with the first capacitor and the first resistor is 50 ns or less.

12. The ESD protection circuit of claim 1 , wherein the trigger circuit includes:
a first trigger circuit transistor connected between the protected pad and the first control node;
a second trigger circuit transistor connected between the first control node and the voltage supply node;
a first capacitor connected between the protected pad and a control terminal of the first trigger circuit transistor;
a first resistor connected between the control terminal of the first trigger circuit transistor and the voltage supply node;
a second resistor connected between the first control node and the voltage supply node; and
a third trigger circuit transistor connected between the control terminal of the first trigger circuit transistor and the voltage supply node;
wherein control terminals of the second and third trigger circuit transistors are connected to a second voltage supply node; and
wherein a trigger circuit time constant associated with the first capacitor and the first resistor corresponds to the first slew rate.

13. An integrated circuit (IC), comprising:
a conductive pad to electrically connect an internal circuit of the IC with an external circuit; and
a protection circuit to protect the internal circuit connected to the conductive pad, the protection circuit including:
a first transistor, including a first drain terminal coupled with the conductive pad, a first source terminal coupled with a voltage supply node, and a first control terminal coupled to a first control node,
a trigger circuit to turn on the first transistor to conduct a current from the conductive pad to the voltage supply node in response to a first voltage rise in the conductive pad at or above a first slew rate, and

a second circuit coupled between the first control node and the voltage supply node, the second circuit configured to reduce the voltage of the first control node in response to a second voltage rise in the first control node at a second slew rate below the first slew rate, the reduced voltage of the first control node partially reducing the current flow through the first transistor, the second circuit comprising:
a low pass filter circuit to provide a rising filter output signal at a first filter node responsive to the rises in the voltage of the first control node, the low pass filter circuit including a first filter resistor connected between the first control node and the first filter node, and a first filter capacitor connected between the first filter node and the voltage supply node, a filter time constant associated with the first filter resistor and the first filter capacitor of the low pass filter circuit is between 100 ns and 2 μs.

14. The IC of claim 13 , wherein the second circuit includes:
a second transistor, i

Assignees

• Texas Instruments Inc

Inventors

• Chen Zhong
• Wang Liang

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H9/004

  in connection with live-insertion of plug-in units (involving communication with a central processing unit G06F13/40) · CPC title

• H02H3/22

  of short duration, e.g. lightning · CPC title