PSTTM device with bottom electrode interface material

Patent metadata

Field	Value
Publication number	US-10340445-B2
Application number	US-201515755446-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.

First claim

What is claimed is:

1. A magnetic tunneling junction (MTJ) material layer stack over a substrate, the stack comprising:
one or more electrode interface material layers comprising Ta or CoFeB over a first electrode metal;
a seed layer comprising Pt over the electrode interface material layers;
a synthetic antiferromagnet (SAF) stack over the seed layer;
a fixed magnetic material layer between the SAF and a free magnetic material layer; and
a dielectric material layer between the fixed magnetic material layer and the free magnetic material layer.

2. The material stack of claim 1 , wherein the one or more electrode interface material layers comprising Ta or CoFeB have a thickness no more than 5 nm.

3. The material stack of claim 2 , wherein the one or more electrode interface material layers consist of a single layer of Ta having a thickness less than 2 nm.

4. The material stack of claim 1 , wherein the one or more electrode interface material layers comprise:
a Ta material layer comprising Ta; and
a CoFeB material layer comprising CoFeB, or a Ru material layer comprising Ru.

5. The material stack of claim 4 , wherein the one or more electrode interface material layers comprise:
the CoFeB material layer, which is in direct contact with the seed layer; and
the Ta material layer between the CoFeB material layer and the first electrode metal.

6. The material stack of claim 5 , wherein:
the CoFeB material layer has a thickness of 0.5-5 nm; and
the Ta material layer is at least predominantly Ta and has a thickness of 1-5 nm.

7. The material stack of claim 5 , wherein the CoFeB material layer has the same composition as at least one of the fixed magnetic material layer, or the free magnetic material layer.

8. The material stack of claim 1 , wherein the one or more electrode interface material layers comprise: a CoFeB material layer comprising CoFeB in direct contact with the seed layer.

9. The material stack of claim 8 , wherein the CoFeB material is also in direct contact with the first electrode metal.

10. The material stack of claim 4 , wherein the one or more electrode interface material layers comprise:
the Ta material layer comprising Ta, which is in direct contact with the seed layer; and
the Ru material layer comprising Ru, which is between the Ta material layer and the first electrode metal.

11. The material stack of claim 10 , wherein:
the Ta material layer is at least predominantly Ta and has a thickness of 1-5 nm; and
the Ru material layer is at least predominantly Ru and has a thickness of 10-20 nm.

12. The material stack of claim 1 , wherein:
the first electrode metal comprises Ti;
the SAF stack includes a superlattice comprising a plurality of Co/Pt bilayers;
the magnetic material layers comprise a CoFeB material and have perpendicular magnetic anisotropy; and
the dielectric material layer comprises an oxide of Mg.

13. A non-volatile memory device, comprising:
a first electrode;
a second electrode coupled to first interconnect metallization of the memory array;
a MTJ material stack between the first and second electrodes, wherein the MTJ material stack further comprises:
one or more electrode interface material layers comprising Ta or a CoFeB material over a first electrode metal;
a seed layer comprising Pt disposed over the one or more electrode interface material layers;
a synthetic antiferromagnet (SAF) stack over the seed layer;
a fixed magnetic material layer between the SAF and a free magnetic material layer; and
a dielectric material layer between the fixed magnetic material layer and the free magnetic material layer; and

a transistor with a first terminal electrically coupled to the first electrode, a second terminal electrically coupled to a second interconnect metallization of the memory array, and a third terminal electrically coupled to a third interconnect metallization of the memory array.

14. The memory device of claim 13 , wherein:
the one or more electrode interface material layers comprise the CoFeB material in direct contact with the seed layer, and the Ta material layer between the CoFeB material and the first electrode metal;
the first electrode metal comprises Ti;
the SAF stack includes a superlattice comprising a plurality of Co/Pt bilayers;
the magnetic material layers also comprise CoFeB and have perpendicular magnetic anisotropy; and
the dielectric material layer comprises MgO.

15. The memory device of claim 13 , wherein:
the one or more electrode interface material layers comprise the Ta material layer in direct contact with the seed layer, and a Ru material layer disposed between the CoFeB material layer and the first electrode metal;
the first electrode metal comprises Ti;
the SAF stack includes a superlattice comprising a plurality of Co/Pt bilayers;
the magnetic material layers also comprise CoFeB and have perpendicular magnetic anisotropy; and
the dielectric material layer comprises MgO.

16. A mobile computing platform comprising:
a non-volatile memory comprising a plurality of the non-volatile memory cell of claim 13 ;
a processor communicatively coupled to the non-volatile memory;
a battery coupled to the processor; and
a wireless transceiver.

Assignees

• Intel Corp

Inventors

• Oguz Kaan
• O'Brien Kevin P
• Wiegand Christopher J
• Rahman Md Tofizur
• Doyle Brian S
• Doczy Mark L
• Golonzka Oleg
• Ghani Tahir
• Brockman Justin S

Classifications

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01F10/30 Primary

  characterised by the composition of the intermediate layers {, e.g. seed, buffer, template, diffusion preventing, cap layers (H01F10/06 and H01F10/32 take precedence)} · CPC title