Semiconductor device and method for producing the same

Patent metadata

Field	Value
Publication number	US-10340390-B2
Application number	US-201615569422-A
Country	US
Kind code	B2
Filing date	Jun 2, 2016
Priority date	Jun 8, 2015
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer. The percentage of Sn having a metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to the total amount of Sn. A region where the percentage is 50% or more has a thickness of less than 10 nm.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate, a thin-film transistor supported on the substrate, and a first insulating layer,
the thin-film transistor including a semiconductor layer, a gate electrode, a gate insulating layer arranged between the gate electrode and the semiconductor layer, a source electrode, and a drain electrode, the source electrode and the drain electrode being in contact with the semiconductor layer, wherein
one of an upper surface and a lower surface of the semiconductor layer is in contact with the gate insulating layer, the other is in contact with the first insulating layer,
the semiconductor layer has a laminated structure including a first oxide semiconductor layer and a second oxide semiconductor layer, the first oxide semiconductor layer is arranged on a gate insulating layer side of the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer,
the first insulating layer contains silicon oxide,
the second oxide semiconductor layer contains In and Ga and does not contain Sn,
the first oxide semiconductor layer contains In, Sn, and Zn,
a percentage of Zn in the first oxide semiconductor layer in a depth direction does not have a maximum value in a vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer,
a percentage of Sn having a metallic bonding state at an interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to a total amount of Sn, and
a region where the percentage of Sn having the metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 50% or more with respect to the total amount of Sn has a thickness of less than 10 nm.

2. The semiconductor device according to claim 1 , wherein the percentage of Sn having the metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 40% or less with respect to the total amount of Sn.

3. The semiconductor device according to claim 1 , wherein a composition ratio of Ga contained in the second oxide semiconductor layer is higher than a composition ratio of In contained in the second oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer is in contact with the gate insulating layer, and a percentage of Zn having a metallic bonding state at an interface between the first oxide semiconductor layer and the gate insulating layer is 50% or less with respect to a total amount of Zn.

5. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer is in contact with the first insulating layer, and
a percentage of oxygen in the second oxide semiconductor layer in the depth direction does not have a minimum value in a vicinity of a surface of the second oxide semiconductor layer adjacent to the first insulating layer.

6. The semiconductor device according to claim 1 , wherein a percentage of In having a metallic bonding state in the second oxide semiconductor layer is 10% or more with respect to a total amount of In, and
the percentage of In having the metallic bonding state in the first oxide semiconductor layer is less than 10% with respect to the total amount of In.

7. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer contains an In—Sn—Zn—O-based semiconductor.

8. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer contains an In—Ga—Zn—O-based semiconductor.

9. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer contains an In—Ga—O-based semiconductor.

10. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer contains a crystalline portion.

11. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer is in contact with the gate insulating layer, and the second oxide semiconductor layer is in contact with the first insulating layer.

12. The semiconductor device according to claim 1 , wherein the gate electrode is arranged between the semiconductor layer and the substrate,
each of the source electrode and the drain electrode is in contact with part of the upper surface of the semiconductor layer, and
the first insulating layer is a protective film covering the thin-film transistor and is in contact with a portion of the upper surface of the semiconductor layer located between the source electrode and the drain electrode.

13. The semiconductor device according to claim 1 , wherein the gate electrode is arranged between the semiconductor layer and the substrate,
each of the source electrode and the drain electrode is in contact with part of the upper surface of the semiconductor layer, and
the first insulating layer is arranged between the semiconductor layer and the source electrode and the drain electrode, and the first insulating layer is in contact with a portion of the upper surface of the semiconductor layer located between the source electrode and the drain electrode.

14. The semiconductor device according to claim 1 , further comprising a third oxide semiconductor layer between the first oxide semiconductor layer and the gate insulating layer, wherein the third oxide semiconductor layer contains In and Ga and does not contain Sn.

15. A method for producing a semiconductor device, comprising the steps of:
(A) forming a gate electrode and a gate insulating layer covering the gate electrode on a substrate;
(B) forming a semiconductor layer having a laminated structure on the gate insulating layer, the semiconductor layer including a first oxide semiconductor layer and a second oxide semiconductor layer, the step (B) including the substeps of:
forming the first oxide semiconductor layer containing In, Sn, and Zn; and
forming the second oxide semiconductor layer that contains In and Ga and that does not contain Sn so as to be in contact with an upper surface of the first oxide semiconductor layer;

(C) forming a source electrode and a drain electrode in contact with the semiconductor layer to provide a thin-film transistor; and
(D) forming a first insulating layer containing silicon oxide so as to cover the thin-film transistor, wherein
after the step (D), the method further comprises a step of subjecting the substrate including the semiconductor layer to annealing treatment at a temperature of 300° C. or lower,
a percentage profile of Zn in the first oxide semiconductor layer in a depth direction does not have a maximum value in a vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer,
a percentage of Sn having a metallic bonding state at an interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to a total amount of Sn, and
a region where the percentage of Sn having the metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 50% or more with respect to the total amount of Sn has a thickness of less than 10 nm.

16. The method for producing a semiconductor device according to claim 15 , wherein a composition ratio of Ga contained in the second oxide semiconductor layer is higher than a composition ratio of In contained in the second oxide semiconductor layer.

17. The method for producin

Assignees

• Sharp Kk

Inventors

• Kanzaki Yohsuke
• Saitoh Takao
• Takamaru Yutaka
• Ide Keisuke
• Kaneko Seiji

Classifications

• H01L29/786

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic