CMOS image sensor

US10340304B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10340304-B2
Application numberUS-201816019281-A
CountryUS
Kind codeB2
Filing dateJun 26, 2018
Priority dateJan 7, 2016
Publication dateJul 2, 2019
Grant dateJul 2, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.

First claim

Opening claim text (preview).

What is claimed is: 1. A CMOS image sensor, comprising: a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region, wherein the third implanting region and the fourth implanting region have side surfaces coinciding with an edge of the transfer transistor. 2. The CMOS image sensor according to the claim 1 , further comprising: a sixth implanting region formed in the surface of the substrate in a second region overlapping a portion of a first region and a portion of the surface of the substrate adjacent to first region. 3. The CMOS image sensor according to claim 1 , further comprising: a pinning layer covering the third implanting region, the floating diffusion layer and the surface of the substrate. 4. The CMOS image sensor according to claim 1 , wherein: the substrate has a first conductive type; the first implanting region has a second conductive type opposite to the first conductive type; the second implanting region has the first conductive type; the third implanting region and the fourth implanting region have the second conductive type; and the fifth implanting region has the second conductive type. 5. The CMOS imaging sensor according to claim 4 , wherein: the first implanting region is formed by a first ion implantation process, a second ion implantation process and a third ion implantation process. 6. The CMOS imaging sensor according to claim 4 , wherein: a conductive type of ions of the first ion implantation process, the second ion implantation process and the third ion implantation process is the second conductive type. 7. The CMOS imaging sensor according to claim 5 , wherein: energies of the first ion implantation process, the second ion implantation process and the third ion implantation process are gradually increased. 8. The CMOS imaging sensor according to claim 1 , wherein: ions implanted in the second implanting region are boron ions; an energy of the ion plantation process for forming the second implanting region is approximately 160 KeV; and a dosage of boron ions is approximately 3.5E12 atom/cm 2 . 9. The CMOS imaging sensor according to claim 1 , wherein: ions implanted in the fifth implanting region are phosphor ions; an energy of the ion implantation process for forming the fifth implanting region is approximately 250 KeV; and a dosage of phosphor ions is approximately 3E12 atom/cm 2 . 10. The CMOS imaging sensor according to claim 1 , further including: a pinning layer formed in the surface of the substrate by an ion implantation process. 11. The CMOS imaging sensor according to claim 10 , wherein: ions of the ion implantation process are BF 2 ions; an energy of the ion implantation process is approximately 30 KeV; and a dosage of the BF 2 ions is approximately 5E12 atom/cm 2 . 12. The CMOS imaging sensor according to claim 1 , further including: a sixth implanting region formed in the surface of the substrate by an ion implantation process using the second mask. 13. The CMOS imaging sensor according to claim 12 , wherein: ions of the ion implantation process are BF 2 ions; an energy of the ion implantation process is approximately 30 KeV; and a dosage of BF 2 ions is approximately 5E12 atom/cm 2 . 14. The CMOS image sensor according to the claim 2 , wherein: the third implanting region, the fourth implanting region, and the fifth implanting region form a U-shaped implanting region. 15. The CMOS image sensor according to the claim 14 , wherein: the sixth implanting region covers the U-shaped implanting region and isolates the U-shaped implanting region from a channel region under the transfer transistor. 16. The CMOS image sensor according to the claim 2 , wherein: the sixth implanting region has a side surface coinciding with the side surfaces of the third implanting region and the fourth implanting region. 17. The CMOS image sensor according to the claim 1 , wherein: the fifth implanting region protrudes from the side surfaces of the third implanting region and the fourth implanting region.

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What does patent US10340304B2 cover?
The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor…
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai Corp, Semiconductor Mfg Int Beijing Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/14643. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 02 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).