Semiconductor device

Patent metadata

Field	Value
Publication number	US-10340291-B2
Application number	US-201715721901-A
Country	US
Kind code	B2
Filing date	Sep 30, 2017
Priority date	Nov 15, 2016
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including a main surface and a back surface;
a first semiconductor region of a first conductivity type formed in the semiconductor substrate;
a first active region and a second active region whose peripheries are defined by an element isolation region, in the first semiconductor region;
a first semiconductor layer formed on the main surface of the semiconductor substrate via a first insulating film, in the first active region;
a first gate electrode formed on a surface of the first semiconductor layer via a first gate insulating film;
a first sidewall spacer formed on a side wall of the first gate electrode;
first epitaxial layers formed on the first semiconductor layer at both sides of the first gate electrode;
a second semiconductor region and a third semiconductor region of a second conductivity type formed in the first semiconductor layer and the first epitaxial layers at both sides of the first gate electrode, the second conductivity type being a conductivity type opposite to the first conductivity type;
a fourth semiconductor region of the first conductivity type formed below the first insulating film, in the first active region;
a first silicide layer formed on a surface of the first semiconductor region, in the second active region;
an interlayer insulating film covering the first gate electrode; and
a first power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the second active region extends in a first direction,
wherein, in a plan view, the first power supply wiring extends in the first direction so as to overlap with the second active region,
wherein the first power supply wiring is connected to the second semiconductor region,
wherein the first gate electrode extends in a second direction perpendicular to the first direction, and lies on the element isolation region between the first active region and the second active region, and
wherein the first silicide layer is connected to the first power supply wiring.

2. The semiconductor device according to claim 1 ,
wherein an interface between the first silicide layer and the first semiconductor region is closer to the back surface of the semiconductor substrate than an interface between the first insulating film and the fourth semiconductor region.

3. The semiconductor device according to claim 1 , further comprising
a fifth semiconductor region of the second conductivity type formed below the first sidewall spacer in the first semiconductor layer.

4. The semiconductor device according to claim 3 ,
wherein an impurity concentration of each of the second semiconductor region and the third semiconductor region is higher than an impurity concentration of the fifth semiconductor region.

5. The semiconductor device according to claim 1 ,
wherein the first conductivity type is an N-type, and the second conductivity type is a P-type.

6. The semiconductor device according to claim 1 , further comprising:
a sixth semiconductor region of the second conductivity type formed in the semiconductor substrate;
a third active region and a fourth active region whose peripheries are defined by the element isolation region in the sixth semiconductor region;
a second semiconductor layer formed on the main surface of the semiconductor substrate via a second insulating film in the third active region;
a second gate electrode formed on a surface of the second semiconductor layer via a second gate insulating film;
a second sidewall spacer formed on a side wall of the second gate electrode;
second epitaxial layers formed on the second semiconductor layer at both sides of the second gate electrode;
a seventh semiconductor region and an eighth semiconductor region of the first conductivity type formed in the second semiconductor layer and the second epitaxial layers at both sides of the second gate electrode;
a ninth semiconductor region of the second conductivity type formed below the second insulating film in the third active region;
a third epitaxial layer formed on the sixth semiconductor region in the fourth active region;
a second silicide layer formed on a surface of the third epitaxial layer;
the interlayer insulating film covering the second gate electrode; and
a second power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the fourth active region extends in the first direction,
wherein, in a plan view, the second power supply wiring extends in the first direction so as to overlap with the fourth active region,
wherein the second power supply wiring is connected to the seventh semiconductor region, and
wherein the second gate electrode extends in the second direction, and lies on the element isolation region between the third active region and the fourth active region.

7. The semiconductor device according to claim 6 ,
wherein the second silicide layer is connected to the second power supply wiring.

8. The semiconductor device according to claim 6 ,
wherein an interface between the second silicide layer and the third epitaxial layer is farther from the back surface of the semiconductor substrate than an interface between the second insulating film and the ninth semiconductor region.

9. The semiconductor device according to claim 6 ,
wherein, in a plan view, the first active region and the third active region are arranged in the second direction, and are sandwiched between the second active region and the fourth active region extending in the first direction.

10. A semiconductor device comprising:
a semiconductor substrate including a main surface and a back surface;
a first semiconductor region of a first conductivity type formed in the semiconductor substrate;
a first active region and a second active region whose peripheries are defined by an element isolation region, in the first semiconductor region;
a first semiconductor layer formed on the main surface of the semiconductor substrate via a first insulating film, in the first active region;
a first gate electrode formed on a surface of the first semiconductor layer via a first gate insulating film;
a first sidewall spacer formed on a side wall of the first gate electrode;
first epitaxial layers formed on the first semiconductor layer at both sides of the first gate electrode;
a second semiconductor region and a third semiconductor region of a second conductivity type formed in the first semiconductor layer and the first epitaxial layers at both sides of the first gate electrode, the second conductivity type being a conductivity type opposite to the first conductivity type;
a fourth semiconductor region of the first conductivity type formed below the first insulating film, in the first active region;
a first silicide layer formed on a surface of the first semiconductor region, in the second active region;
an interlayer insulating film covering the first gate electrode; and
a first power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the second active region extends in a first direction,
wherein, in a plan view, the first power supply wiring extends in the first direction so as to overlap with the second active region,
wherein the first power supply wiring is connected to the second semiconductor region,
wherein the first gate electrode extends in a second direction perpendicular to the first direction, and lies on the element isolation region between the first active region and the second active region,
wherein the semiconductor device further comprises:
a sixth semiconductor region of the second conductivity type formed in the semiconductor substrat

Assignees

• Renesas Electronics Corp

Inventors

• Tsuboi Nobuo
• Yamamoto Yoshiki

Classifications

• G05F1/625

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H01L27/1244

  Electricity · mapped topic

• H01L27/02

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic