Ray tracing apparatus and method

Patent metadata

Field	Value
Publication number	US-10339694-B2
Application number	US-201614997028-A
Country	US
Kind code	B2
Filing date	Jan 15, 2016
Priority date	Mar 25, 2015
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A ray tracing apparatus includes a ray generator and a traversal (TRV)/intersection test (IST) integrator. The ray generator is configured to generate a ray. The TRV/IST integrator is configured to receive the ray, determine one of a ray-node intersection test, an intersection distance test, and a hit point test to be performed based on a state of the ray input thereto, and perform the determined test with respect to the ray. The ray-node intersection test, the intersection distance test, and the hit point test are performed with respect to the ray through same pipeline.

First claim

What is claimed is:

1. A ray tracing apparatus comprising:
a ray generator configured to generate a ray and transmit the ray; and
an unified traversal (TRV)/intersection test (IST) processor configured to
receive the ray,
determine one of a ray-node intersection test, an intersection distance test, and a hit point test to be performed based on a state of the ray thereto, and
perform the determined test with respect to the ray,

wherein the unified TRV/IST processor is configured to perform the ray-node intersection test, the intersection distance test, and the hit point test with respect to the ray through a same pipeline, the pipeline including a plurality of stages, each of the stages including at least one arithmetic unit configured to perform processing for each of the ray-node intersection test, the intersection distance test, and the hit point test of the corresponding stage, and
determine the at least one arithmetic unit to be used at each of the stages based on a hardware area occupied by each of the at least one arithmetic unit.

2. The ray tracing apparatus of claim 1 , further comprising:
a ray state updater configured to update the state of the ray received from the unified TRV/IST processor based on a result obtained by performing the determined test and transmit the ray to the unified TRV/IST processor.

3. The ray tracing apparatus of claim 2 , wherein, the ray state updater is configured to:
update the state of the ray so as not to perform the hit point test between the ray and a first primitive intersected by the ray, when a distance from the ray to the first primitive is determined not to be a valid distance as a result of the intersection distance test.

4. The ray tracing apparatus of claim 2 , wherein, the ray state updater is configured to:
update the state of the ray so as to perform the hit point test between the ray and a first primitive intersected by the ray, when a distance from the ray to the first primitive is determined to be valid distance as a result of the intersection distance test.

5. The ray tracing apparatus of claim 1 , wherein the unified TRV/IST processor is further configured to:
perform at least one arithmetic operation included in the ray-node intersection test, at least one arithmetic operation included in the intersection distance test, and at least one arithmetic operation included in the hit point test via the same arithmetic unit in at least one stage included in the same pipeline.

6. The ray tracing apparatus of claim 1 , further comprising:
a shader configured to
receive a hit point between the ray and a primitive intersected by the ray, and
determine a color value of a pixel based on the hit point.

7. The ray tracing apparatus of claim 1 , further comprising:
a TRV processor configured to perform only the ray-node intersection test.

8. The ray tracing apparatus of claim 7 , further comprising:
a ray dispatcher configured to determine whether to transmit the ray to the TRV processor or the unified TRV/IST processor based on the state of the ray and workloads of the TRV processor and the unified TRV/IST processor.

9. A ray tracing method comprising:
generating a ray at a ray generator;
inputting the ray to an unified traversal (TRV)/intersection test (IST) processor;
determining, at the unified TRV/IST processor, one of a ray-node intersection test, an intersection distance test, and a hit point test based on a state of the ray; and
performing, at the unified TRV/IST processor, the determined test with respect to the ray,
wherein the at the unified TRV/IST processor is configured to perform the ray-node intersection test, the intersection distance test, and the hit point test with respect to the ray through a same pipeline, the pipeline including a plurality of stages, each of the stages including at least one arithmetic unit configured to perform processing for each of the ray-node intersection test, the intersection distance test, and the hit point test of the corresponding stage, and
determine the at least one arithmetic unit to be used at each of the stages based on a hardware area occupied by each of the at least one arithmetic unit.

10. The ray tracing method of claim 9 , further comprising:
updating, at a ray state updater, the state of the ray received from the unified TRV/IST processor, based on a result obtained by performing the determined test; and
transmitting the ray to the unified TRV/IST processor.

11. The ray tracing method of claim 10 , wherein the updating of the state of the ray comprises updating the state of the ray so as not to perform the hit point test between the ray and a first primitive, when a distance from the ray to the first primitive intersected by the ray is determined not to be a valid distance as a result of the intersection distance test.

12. The ray tracing method of claim 10 , wherein the updating of the state of the ray comprises updating the state of the ray so as to perform the hit point test between the ray and a first primitive when a distance from the ray to the first primitive intersected by the ray is determined to be a valid distance as a result of the intersection distance test.

13. The ray tracing method of claim 9 , wherein at least one arithmetic operation included in the ray-node intersection test, at least one arithmetic operation included in the intersection distance test, and at least one arithmetic operation included in the hit point test are performed via the same arithmetic unit in at least one stage included in the same pipeline.

14. The ray tracing method of claim 9 , further comprising:
performing shading at a shader by determining a color value of a pixel based on a hit point between the ray and a primitive intersected by the ray, the hit point being calculated as a result of the hit point test.

15. The ray tracing method of claim 9 , further comprising:
performing the ray-node intersection test through a pipeline other than the same pipeline.

16. The ray tracing method of claim 15 , further comprising:
determining, at a ray dispatcher, whether the ray is to be transmitted to a TRV processor or the unified TRV/IST processor, based on the state of the ray and workloads of the TRV processor including the pipeline other than the same pipeline and the unified TRV/IST processor including the same pipeline.

17. A non-transitory computer-readable recording medium having recorded thereon a program configured to execute the method of claim 9 on a computer.

18. A ray tracing apparatus comprising:
a ray generator configured to generate a ray; and
a ray dispatcher configured to transmit the ray to a traversal (TRV) processor configured to perform, with respect to the ray, only a ray-node intersection test, or
an unified TRV/intersection test (IST) processor configured to perform, with respect to the ray, one of the ray-node intersection test, an intersection distance test, and a hit point test, through a same pipeline, the pipeline including a plurality of stages, each of the stages including at least one arithmetic unit configured to perform processing for each of the ray-node intersection test, the intersection distance test, and the hit point test of the corresponding stage, and
determine the at least one arithmetic unit to be used at each of the stages based on a hardware area occupied by each of the at least one arithmetic unit;

wherein the ray dispatcher is configured to determine whether to transmit the ray to the TRV processor or the unified TRV/IST processor based on a state of the ray and workloads of t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Youngsam
• Lee Wonjong
• Hwang Seokjoong

Classifications

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title