Packet data processing method, apparatus, and system

Patent metadata

Field	Value
Publication number	US-10339091-B2
Application number	US-201615344972-A
Country	US
Kind code	B2
Filing date	Nov 7, 2016
Priority date	May 8, 2014
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A packet data processing method, apparatus, and system. The method is executed by a first processing apparatus, and includes: acquiring packet data that needs to be processed, where the packet data that needs to be processed includes first packet data information and second packet data, and the first packet data information includes a header of the packet data that needs to be processed and a storage address of the packet data that needs to be processed in the first processing apparatus; sending the first packet data information to a second processing apparatus; and receiving first packet data information (includes an updated header after being processed and the storage address) processed by the second processing apparatus, and generating finished packet data using the first packet data information processed by the second processing apparatus and the second packet data.

First claim

What is claimed is:

1. A packet data processing method executed by a first processing apparatus, the method comprising:
acquiring, by the first processing apparatus, first packet data that needs to be processed, the first packet data that needs to be processed comprising first packet data information and second packet data stored at a first storage address in the first processing apparatus, and the first packet data information comprising a header of the first packet data and the first storage address of the second packet data;
sending, by the first processing apparatus to a second processing apparatus, the first packet data information including the first storage address in the first processing apparatus at which the second packet data is stored;
receiving, by the first processing apparatus from the second processing apparatus, first updated packet data information that comprises a first updated header and the first storage address in the first processing apparatus at which the second packet data is stored;
subsequent to receiving the first updated packet data information from the second processing apparatus, acquiring, by the first processing apparatus, the second packet data using the first storage address;
processing, by the first processing apparatus, the first updated packet data information and the second packet data to generate first finished packet data by associating the first updated header with the second packet data;
storing the first finished packet data in a second storage address in the first processing apparatus;
acquiring, by the first processing apparatus, the first finished packet data from the second storage address in the first processing apparatus at which the first finished packet data is stored;
sending, by the first processing apparatus to the second processing apparatus, the first updated header and the second storage address in the first processing apparatus at which the first finished packet data is stored;
receiving, by the first processing apparatus from the second processing apparatus, second updated packet data information that comprises a second updated header and the second storage address in the first processing apparatus at which the first finished packet data is stored;
subsequent to receiving the second updated packet data information from the second processing apparatus, acquiring, by the first processing apparatus, the second packet data using the second storage address at which the first finished packet data is stored; and
processing, by the first processing apparatus, the second updated packet data information and the second packet data to generate second finished packet data by associating the second updated header with the second packet data.

2. The packet data processing method of claim 1 , wherein the first processing apparatus communicates with the second processing apparatus using Peripheral Component Interconnect Express.

3. The packet data processing method of claim 1 , wherein the first processing apparatus is a central processing unit and the second processing apparatus is a coprocessor.

4. The packet data processing method of claim 1 , wherein the first processing apparatus is a coprocessor and the second processing apparatus is a central processing unit.

5. The method of claim 1 , wherein the first processing apparatus is an x86 central processing unit and the second processing apparatus is a network interface card.

6. The method of claim 1 , wherein the first storage address is different than the second storage address.

7. A packet data processing method, comprising:
identifying, by a first virtual machine in a central processing unit (CPU), first packet data information in first packet data that needs to be processed, the first packet data information including a header of the first packet data and a first storage address in the first virtual machine at which second packet data of the first packet data is stored;
sending, by the first virtual machine to a coprocessor chip, the first packet data information including the first storage address in the first virtual machine at which the second packet data of the first packet data is stored;
receiving, by the coprocessor chip from the first virtual machine, the first packet data information;
processing, by the coprocessor chip, the header of the first packet data to obtain a first updated header;
sending, by the coprocessor chip to a second virtual machine in the CPU, first updated packet data information that includes the first updated header and the first storage address in the first virtual machine at which the second packet data is stored;
receiving, by the second virtual machine from the coprocessor chip, the first updated packet data information including the first storage address in the first virtual machine at which the second packet data is stored;
subsequent to the second virtual machine receiving the first updated packet data information from the coprocessor chip, acquiring, by the second virtual machine, the second packet data using the first storage address;
processing, by the second virtual machine, the first updated packet data information and the second packet data to generate first finished packet data by associating the first updated header with the second packet data;
storing the first finished packet data in a second storage address in the first virtual machine;
acquiring, by the first virtual machine, the first finished packet data from the second storage address in the first virtual machine at which the first finished packet data is stored;
sending, by the first virtual machine to the coprocessor chip, the first updated header and the second storage address in the first virtual machine at which the first finished packet data is stored;
receiving, by the second virtual machine from the coprocessor chip, second updated packet data information that comprises a second updated header and the second storage address in the first virtual machine at which the first finished packet data is stored;
subsequent to receiving the second updated packet data information from the coprocessor chip, acquiring, by the second virtual machine, the second packet data using the second storage address at which the first finished packet data is stored; and
processing, by the second virtual machine, the second updated packet data information and the second packet data to generate second finished packet data by associating the second updated header with the second packet data.

8. The packet data processing method of claim 7 , wherein the CPU communicates with the coprocessor chip using Peripheral Component Interconnect Express.

9. A packet data processing apparatus, the packet data processing apparatus being located in a first processing apparatus, and the packet data processing apparatus comprising:
a first processor configured to acquire first packet data that needs to be processed, the first packet data comprising first packet data information and second packet data stored at a first storage address in the first processing apparatus, and the first packet data information comprising a header of the first packet data and the first storage address of the second packet data;
a transmitter coupled to the first processor and configured to send to a second processing apparatus the first packet data information including the first storage address in the first processing apparatus at which the second packet data is stored; and
a second processor coupled to the first processor and configured to:
receive, from the second processing apparatus, first updated packet data information that comprises a first updated header and the first storage address in the first processing apparatus at which the second packet data is stored;
subs

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Junying
• Tan Rui

Classifications

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title