Virtual general purpose input/output for a microcontroller

Patent metadata

Field	Value
Publication number	US-10339087-B2
Application number	US-201815901222-A
Country	US
Kind code	B2
Filing date	Feb 21, 2018
Priority date	Sep 27, 2011
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

First claim

What is claimed is:

1. A microcontroller comprising a plurality of general purpose input/output (GPIO) ports,
wherein each GPIO port has a plurality of bits;
wherein each GPIO port comprises a first set of registers for providing at least one of first control and data input/output functionality, wherein each bit of the first set of registers is assigned to a respective external pin and a second set of registers for providing at least one of second control and data input/output functionality of a secondary GPIO port, wherein each register of the second set of registers has a plurality of bits;
a multiplexer and associated select register for controlling the multiplexer to control the respective external pin through either said first or second register set; and
a peripheral pin select circuit which is programmable to assign an external pin to a selectable bit of the second set of registers,
wherein the peripheral pin select circuit is programmed to form a virtual GPIO port controlled by a second set of registers having bits from different GPIO ports mapped to the virtual GPIO port.

2. The microcontroller according to claim 1 , wherein each of the first and second register sets comprises a read register, a write register, and a direction control register.

3. The microcontroller according to claim 2 , wherein each GPIO port comprises for each bit a controllable output driver having an output coupled with an external pin and an input driver having an input coupled with the external pin.

4. The microcontroller according to claim 3 , wherein the first and second read register are coupled for each bit through a first multiplexer with the output of the input driver, the first and second write register are coupled for each bit through a second multiplexer with the input of the output driver, and the first and second direction control register are coupled for each bit through a third multiplexer with a control input of the output driver.

5. The microcontroller according to claim 1 , wherein the secondary GPIO port is remappable wherein bits of the remappable GPIO port are assignable through the peripheral pin select circuit to any bits of any of the GPIO ports.

6. The microcontroller according to claim 5 , wherein bits of the remappable GPIO port correspond to an atomic group of pins.

7. The microcontroller according to claim 1 , further comprising a plurality of peripheral devices, wherein the peripheral pin select circuit is further programmable to assign an external pin to one of the peripheral devices.

8. The microcontroller according to claim 7 , wherein the peripheral devices comprise at least one of an universal asynchronous receiver/transmitter, a serial peripheral interface, and an inter-integrated circuit.

9. The microcontroller according to claim 1 , wherein each GPIO port has 8 bits.

10. A method for operating a microcontroller comprising a plurality of general purpose input/output (GPIO) ports, wherein each port has a plurality of bits, wherein each port comprises a first set of registers for providing at least one of first control and data input/output functionality, wherein each bit of the first set of registers is assigned to a respective external pin and a second set of registers for providing at least one of second control and data input/output functionality of a virtual GPIO port, and a peripheral pin select circuit which is programmable to assign an external pin to one bit of any of the second set of registers, wherein each register of the second set of registers has a plurality of bits, the method comprising:
programming the peripheral pin select circuit to assign bits from different GPIO ports to form the virtual GPIO port; and
when accessing the virtual GPIO port controlling each pin assigned to the virtual GPIO port to switch from an assigned GPIO port to the second register set of the respective pin through respective multiplexers to control respective bits of the virtual GPIO port.

11. The method according to claim 10 , wherein each of the first and second register set comprise a read register, a write register, and a direction control register.

12. The method according to claim 10 , wherein each GPIO port comprises a controllable output driver having an output coupled with an external pin and an input driver having an input coupled with the external pin.

13. The method according to claim 12 , wherein the first and second read register are coupled through a first multiplexer with the output of the input driver, the first and second write register are coupled through a second multiplexer with the input of the output driver, and the first and second direction control register are coupled through a third multiplexer with a control input of the output driver.

14. The method according to claim 10 , wherein the virtual GPIO port is remappable, wherein the method further comprises assigning bits of the virtual GPIO port through the peripheral pin select circuit to any bits of any of the GPIO ports.

15. The method according to claim 14 , wherein bits of the virtual GPIO port correspond to an atomic group of pins.

16. The method according to claim 15 , wherein writing to the virtual GPIO port performs writing to bits from different GPIO ports.

17. The method according to claim 15 , wherein reading the virtual GPIO port performs reading bits from different GPIO ports.

18. The method according to claim 10 , further comprising a plurality of peripheral devices, wherein the method further comprises: programming the peripheral pin select circuit to assign an external pin to one of the peripheral devices.

19. The method according to claim 18 , wherein the peripheral devices comprise at least one of an universal asynchronous receiver/transmitter, a serial peripheral interface, and an inter-integrated circuit.

20. The method according to claim 10 , wherein each GPIO port has eight bits.

21. A method for operating a microcontroller comprising a plurality of general purpose input/output (GPIO) ports, wherein each port has a plurality of bits, wherein each port comprises a first set of registers for providing at least one of first control and data input/output functionality, wherein each bit of the first set of registers is assigned to a respective external pin and a second set of registers for providing at least one of second control and data input/output functionality of a virtual GPIO port, and a peripheral pin select circuit which is programmable to assign an external pin to one bit of any of the second set of registers, wherein each register of the second set of registers has a plurality of bits, the method comprising:
programming the peripheral pin select circuit to assign a first external pin being assigned to a bit of a first GPIO port to be controlled by a one bit of the virtual GPIO port;
programming the peripheral pin select circuit to assign a second external pin being assigned to a bit of a second GPIO port different from the first GPIO port to be controlled by another bit of the virtual GPIO port; and
when accessing the virtual GPIO port controlling the first and second external pin through the second register set.

Assignees

• Microchip Tech Inc
• Microship Tech Incorporated

Inventors

• Simmons Michael

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title