Vector Galois Field Multiply Sum and Accumulate instruction

Patent metadata

Field	Value
Publication number	US-10338918-B2
Application number	US-201715613701-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Jan 23, 2013
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.

First claim

What is claimed is:

1. A computer-implemented method of executing instructions, the computer-implemented method comprising:
obtaining, by a processor, an instruction for execution, the instruction having associated therewith:
an opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation; and
a plurality of operands including a first operand, a second operand, a third operand, and a fourth operand; and
a control to specify a size of elements of the second operand and the third operand, wherein the control is specified by a mask associated with the instruction: and

executing the instruction, the executing comprising:
multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;
performing a first mathematical operation on the plurality of products to obtain a first result;
performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and
placing the second result in the first operand.

2. The computer-implemented method of claim 1 , wherein the multiplying comprises multiplying each element of the second operand with a corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

3. The computer-implemented method of claim 2 , wherein the carryless multiplication has an order of two.

4. The computer-implemented method of claim 2 , wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

5. The computer-implemented method of claim 4 , wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

6. The computer-implemented method of claim 5 , wherein the placing comprises placing the second result in a double-wide element of the first operand.

7. The computer-implemented method of claim 1 , wherein a size of the elements of the first operand and the fourth operand are double the size of the elements of the second operand and the third operand.

8. The computer-implemented method of claim 1 , wherein the instruction has associated therewith an extension field to be used in designating one or more registers, and wherein a first register field of the instruction is combined with a first portion of the extension field to designate a first register, the first register to be used to provide the first operand, a second register field is combined with a second portion of the extension field to designate a second register, the second register to be used to provide the second operand, a third register field is combined with a third portion of the extension field to designate a third register, the third register to be used to provide the third operand, and a fourth register field is combined with a fourth portion of the extension field to designate a fourth register, the fourth register to be used to provide the fourth operand.

9. A computer system for executing instructions, the computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining an instruction for execution, the instruction having associated therewith:
at least one opcode field to provide an opcode, the opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation;
a first register field to be used to designate a first register, the first register comprising a first operand;
a second register field to be used to designate a second register, the second register comprising a second operand;
a third register field to be used to designate a third register, the third register comprising a third operand;
a fourth register field to be used to designate a fourth register, the fourth register comprising a fourth operand; and
an extension field to be used in designating one or more registers, wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register, the third register field is combined with a third portion of the extension field to designate the third register, and the fourth register field is combined with a fourth portion of the extension field to designate the fourth register; and

executing the instruction, the executing comprising:
multiplying one or more elements of the second operand with one or more elements of the third operand using carryless multiplication to obtain a plurality of products;
performing a first mathematical operation on the plurality of products to obtain a first result;
performing a second mathematical operation on the first result and one or more selected elements of the fourth operand to obtain a second result; and
placing the second result in the first operand.

10. The computer system of claim 9 , wherein the multiplying comprises multiplying each element of the second operand with the corresponding element of the third operand using carryless multiplication resulting in even-odd pairs of double element-sized products.

11. The computer system of claim 10 , wherein the carryless multiplication has an order of two.

12. The computer system of claim 10 , wherein the first mathematical operation comprises an exclusive OR operation, and wherein the even-odd pairs of double element-sized products are exclusive ORed with each other to obtain the first result.

13. The computer system of claim 12 , wherein the second mathematical operation comprises an exclusive OR operation, and wherein the first result is exclusive ORed with a corresponding double-wide element of the fourth operand to obtain the second result.

14. The computer system of claim 13 , wherein the placing comprises placing the second result in a double-wide element of the first operand.

15. The computer system of claim 9 , wherein a size of elements of the first operand and the fourth operand are double the size of elements of the second operand and the third operand.

16. The computer system of claim 9 , wherein the machine instruction further comprises a mask field to specify a size of elements of one or more of the first operand, the second operand, the third operand or the fourth operand of the machine instruction.

17. The computer system of claim 9 , wherein the machine instruction further comprises a mask field to specify a size of elements of the second operand and the third operand.

18. A computer program product for executing instructions, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:
obtaining an instruction for execution, the instruction having associated therewith:
at least one opcode field to provide an opcode, the opcode identifying a Vector Galois Field Multiply Sum and Accumulate operation;
a first register field to be used to designate a first register, the first register comprising a first operand;
a second register field to be used to designate a second register, the second register comprising a second operand;
a third register field to be used to designate a third register, t

Assignees

• IBM

Inventors

• Bradbury Jonathan D

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title