Semiconductor device having low resistance source and drain regions

Patent metadata

Field	Value
Publication number	US-10338446-B2
Application number	US-201515535684-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Dec 16, 2014
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A semiconductor device has a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode. A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20 s) or a drain region (20 d) can be reduced, resulting in diminished parasitic capacitance.

First claim

What is claimed is:

1. A display device comprising:
a display portion including a plurality of scanning signal lines formed on an insulating substrate, a plurality of data signal lines crossing each of the scanning signal lines, and a plurality of pixel formation portions disposed in a matrix so as to correspond to intersections of the scanning signal lines and the data signal lines;
a scanning signal line driver circuit configured to sequentially activate and thereby select the scanning signal lines; and
a data signal line driver circuit configured to apply a voltage to the data signal lines in accordance with image data, wherein,
each of the pixel formation portions formed in the display portion includes:
a semiconductor device comprising:
a semiconductor layer formed on an insulating substrate;
a gate insulating film having tapering side surfaces and formed on the semiconductor layer;
a gate electrode having tapering side surfaces and formed on the gate insulating film;
a source region and a drain region formed in the semiconductor layer on opposite sides with respect to the gate electrode;
a silicon nitride film formed on the source region and the drain region of the semiconductor layer; and
a source electrode layer and a drain electrode layer respectively in ohmic contact with the source region and the drain region, wherein,
the source region and the drain region are low-resistance regions formed through reduction caused by hydrogen contained in the silicon nitride film, and
the low-resistance region has a portion with a first length ranging from a first position on the semiconductor layer corresponding to an end of the gate insulating film to a region below the gate electrode, the first length being substantially equal to a second length ranging from the first position to a second position on the semiconductor layer corresponding to an end of the gate electrode; and

a pixel capacitor configured to hold the image data provided via the data signal line by the semiconductor device being switched between on and off states, and

the pixel capacitor is formed above the semiconductor device and includes a first electrode connected to the data signal line via the semiconductor device, a second electrode disposed opposite the first electrode, and an insulating layer sandwiched between the first electrode and the second electrode.

2. A display device comprising:
a display portion including a plurality of scanning signal lines formed on an insulating substrate, a plurality of data signal lines crossing each of the scanning signal lines, and a plurality of pixel formation portions disposed in a matrix so as to correspond to intersections of the scanning signal lines and the data signal lines;
a scanning signal line driver circuit configured to sequentially activate and thereby select the scanning signal lines; and
a data signal line driver circuit configured to apply a voltage to the data signal lines in accordance with image data, wherein,
each of the pixel formation portions formed in the display portion includes:
a semiconductor device comprising:
a semiconductor layer formed on an insulating substrate;
a gate insulating film having tapering side surfaces and formed on the semiconductor layer;
a gate electrode having tapering side surfaces and formed on the gate insulating film;
a source region and a drain region formed in the semiconductor layer on opposite sides with respect to the gate electrode;
a silicon nitride film formed on the source region and the drain region of the semiconductor layer; and
a source electrode layer and a drain electrode layer respectively in ohmic contact with the source region and the drain region, wherein,
the source region and the drain region are low-resistance regions formed through reduction caused by hydrogen contained in the silicon nitride film, and
the low-resistance region has a portion with a first length ranging from a first position on the semiconductor layer corresponding to an end of the gate insulating film to a region below the gate electrode, the first length being substantially equal to a second length ranging from the first position to a second position on the semiconductor layer corresponding to an end of the gate electrode; and

a pixel capacitor configured to hold the image data provided via the data signal line by the semiconductor device being switched between on and off states, and

the pixel capacitor includes a first electrode connected to the data signal line via the semiconductor device, a second electrode disposed opposite the first electrode, and an insulating layer sandwiched between the first electrode and the second electrode, the first electrode being formed on the outside with respect to a drain region formed in the semiconductor layer of the semiconductor device, the second electrode being formed on an insulating film stacked above the semiconductor layer, so as to be opposite the first electrode.

Assignees

• Sharp Kk

Inventors

• Matsukizono Hiroshi

Classifications

• H10P32/17

  characterised by the semiconductor material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/41733

  Electricity · mapped topic

• H01L51/5209

  Electricity · mapped topic