Read-out circuits of image sensors and image sensors including the same

Patent metadata

Field	Value
Publication number	US-10334193-B2
Application number	US-201715415273-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Feb 11, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A read-out circuit of an image sensor includes a ramp signal generator, a bias voltage generator and a conversion circuit. The ramp signal generates a ramp signal that linearly varies at a constant slope. The bias voltage generator generates a bias voltage based on a power supply voltage having a first noise component. The conversion circuit generates a reference voltage based on the bias voltage and the ramp signal, and performs an analog-to-digital conversion on an analog signal from a pixel to generate a digital signal corresponding to the analog signal. The analog signal has second noise component. The bias voltage generator adjusts an alternating current component included in the bias voltage such that a magnitude of a third noise component added to the reference voltage is substantially the same as a magnitude of the second noise component.

First claim

What is claimed is:

1. A read-out circuit of an image sensor, the read-out circuit comprising:
a ramp signal generator configured to generate a ramp signal that linearly varies with a constant slope;
a bias voltage generator configured to generate a bias voltage based on a power supply voltage, the power supply voltage having a first noise component; and
a conversion circuit configured to perform an analog-to-digital conversion on an analog signal from a pixel to generate a digital signal corresponding to the analog signal based on the ramp signal, the analog signal having a second noise component,
wherein the bias voltage generator is configured to adjust an alternating current (AC) component included in the bias voltage so that a magnitude of a third noise component in a reference voltage generated based on the bias voltage and the ramp signal or the third noise component provided from a pixel bias circuit coupled to a column line coupled to the pixel is substantially the same as a magnitude of the second noise component.

2. The read-out circuit of claim 1 , wherein the conversion circuit comprises:
a ramp buffer configured to generate the reference voltage based on the bias voltage and the ramp signal;
a correlated double sampling (CDS) circuit configured to perform a CDS on the analog signal based on the reference voltage to generate a comparison signal; and
a counter configured to generate the digital signal corresponding to the analog signal based on the comparison signal and a count clock signal.

3. The read-out circuit of claim 2 , wherein the ramp buffer comprises a first p-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor and a third PMOS transistor connected in series between the power supply voltage and a ground voltage,
the first PMOS transistor includes a source connected to the power supply voltage, a gate connected to the bias voltage, and a drain connected to the second PMOS transistor,
the second PMOS transistor includes a source connected to the first PMOS transistor, a gate connected to a cascode voltage, and a drain connected to the third PMOS transistor at an output node,
the third PMOS transistor includes a source connected to the third PMOS transistor at the output node, a gate receiving the ramp signal and a drain connected to the ground voltage, and
the reference voltage is provided at the output node.

4. The read-out circuit of claim 2 , wherein the bias voltage generator comprises:
a first current source, connected between the power supply voltage and a first node, the first current source configured to generate a first current;
a current mirror circuit, connected to the first node, a ground voltage and a second node, the current mirror circuit configured to output a second current to the second node, wherein the second current corresponds to a sum of a first sub-current and a second sub-current, and the first sub-current is proportional to the first current; and
a p-channel metal oxide semiconductor (PMOS) transistor, connected between the power supply voltage and the second node, the PMOS transistor configured to provide the conversion circuit with the bias voltage based on the second current,
wherein the current mirror circuit is configured to adjust a magnitude of the AC component by adjusting a ratio of a first magnitude of the first sub-current and a second magnitude of the second sub-current.

5. The read-out circuit of claim 4 , wherein the current mirror circuit comprises:
a first n-channel metal oxide semiconductor (NMOS) transistor that has a drain and a gate coupled to the first node, and a source coupled to the ground voltage;
a first current generation circuit connected between the first node, the second node and the ground voltage, wherein the first current generation circuit is configured to generate the first sub-current having the first magnitude which varies in response to a first switching control signal; and
a second current generation circuit connected in parallel with the first current generation circuit between the second node and the ground voltage, wherein the second current generation circuit is configured to generate the second sub-current having the second magnitude which varies in response to a second switching control signal.

6. The read-out circuit of claim 5 , wherein the first current generation circuit comprises:
a plurality of first switches each connected to the second node; and
a plurality of second NMOS transistors respectively connected in series between corresponding ones of the first switches and the ground voltage,
wherein the second current generation circuit comprises
a plurality of second switches each connected to the second node; and
a plurality of second current sources respectively connected in series between corresponding ones of the second switches and the ground voltage, and
wherein each gate of the second NMOS transistors is coupled to the gate of the first NMOS transistor at the first node, and
the first magnitude of the first sub-current and the second magnitude of the second sub-current are adjustable.

7. The read-out circuit of claim 2 , wherein the bias voltage generator comprises:
a current source, connected between the power supply voltage and a first node, the current source configured to generate a first current;
a current mirror circuit, connected to the first node, a ground voltage and a second node, the current mirror circuit configured to output a second current to the second node;
a p-channel metal oxide semiconductor (PMOS) transistor, connected between the power supply voltage and the second node, the PMOS transistor configured to provide the bias voltage based on the second current;
a sampling switch connected between the second node and a third node, wherein the sampling switch is switched in response to a sampling control signal;
a first sampling bank connected between the power supply voltage and the third node, wherein the first sampling bank is configured to sample a first portion of the bias voltage in response to a first switching control signal; and
a second sampling bank connected between the third node and the ground voltage, wherein the second sampling bank is configured to sample a second portion of the bias voltage in response to a second switching control signal.

8. The read-out circuit of claim 7 , wherein the first sampling bank comprises:
a plurality of first capacitors each connected to the power supply voltage; and
a plurality of first switches respectively connected in series between corresponding ones of the first capacitors and the third node,
wherein the second sampling bank comprises
a plurality of second switches each connected to the third node; and
a plurality of second capacitors respectively connected in series between corresponding ones of the second switches and the ground voltage,
wherein the plurality of first switches are switched in response to the first switching control signal, and the plurality of second switches are switched in response to the second switching control signal, and
wherein a magnitude of the AC component is adjusted by the first portion and the second portion of the bias voltage.

9. The read-out circuit of claim 2 , wherein the bias voltage generator comprises:
a current source, connected between the power supply voltage and a first node, the current source configured to generate a first current;
a switched current mirror circuit, connected to the first node, the power supply voltage, a ground voltage and a third node, the switched current mirror circuit configured to output a second current proportional to the first current to the third node when a sampling switch therein is turned on; and
a p-channel met

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Kyu-Ik
• Kim Ji-Yong
• Park Jae-Jung

Classifications

• H03K4/50 Primary

  in which a sawtooth voltage is produced across a capacitor · CPC title

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N5/357

  Electricity · mapped topic

• H04N5/378

  Electricity · mapped topic