Integrated circuitry

Patent metadata

Field	Value
Publication number	US-10333464-B2
Application number	US-201715456277-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Mar 11, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.

First claim

The invention claimed is:

1. Integrated circuitry, comprising:
a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on said clock signal; and
an AC coupling capacitor connected in series along the clock path,
wherein:
the integrated circuitry has a layered structure comprising a plurality of metal layers and one or more via layers sandwiched between adjacent said metal layers;
the clock path is implemented in at least one of said metal layers; and
the AC coupling capacitor is implemented in a said via layer,
wherein portions of the clock path are implemented over one another in an overlapped configuration, and wherein the AC coupling capacitor is provided between the overlapped portions,
and wherein the coupling capacitor is distributed along a length of the overlapped portions.

2. The integrated circuitry of claim 1 , wherein:
the clock path is implemented across adjacent said metal layers, and wherein the AC coupling capacitor is implemented in a said via layer between two adjacent said metal layers across which the clock path is implemented; or
the clock path is implemented in a single said metal layer and wherein the AC coupling capacitor is implemented in a said via layer adjacent to that metal layer.

3. The integrated circuitry of claim 1 , wherein the AC coupling capacitor comprises a dielectric sandwiched between outer plates, and wherein said dielectric outer plates are implemented in the same via layer.

4. The integrated circuitry of claim 1 , wherein the AC coupling capacitor underlies or overlies part of the clock path so as not to take up, additional area either side of the clock path in said layers.

5. The integrated circuitry of claim 1 , comprising a plurality of said clock paths having respective said AC coupling capacitors connected therealong in series.

6. Digital-to-analogue converter circuitry or analogue-to-digital converter circuitry or an IC chip, comprising the integrated circuitry of claim 1 .

7. The integrated circuitry of claim 1 , further comprising:
clock buffer circuitry provided along said clock path for buffering said clock signal; and
a tuneable inductance connected to said clock path.

8. The integrated circuitry of claim 7 , wherein the tuneable inductance comprises an array of inductors and switching circuitry configured to switch the inductors into or out of circuit based upon a control signal.

9. The integrated circuitry of claim 8 , wherein the inductors of the array have mutually different inductance values.

10. The integrated circuitry of claim 8 wherein:
the array has N inductors L 1 to L N , where N is an integer greater than 1;
the inductors have respective inductance values L 1 to L N ; and
the inductance values are set such that different combinations of those inductors provide a range of different overall inductance values of said tuneable inductance, each said combination comprising at least one of those inductors switched into circuit and up to N−1 of those inductors switched out of circuit.

11. The integrated circuitry of claim 10 , wherein:
said range of different, overall inductance values includes a maximum overall inductance value L MAX and a minimum overall inductance value L MIN , and
the inductance values L 1 to L N are set such that said different overall inductance values are substantially evenly distributed from L MAX to L MIN .

12. The integrated circuitry of claim 7 , further comprising:
a tuneable clock source configured to generate said clock signal; and
control circuitry operable to control the tuneable clock source such that said clock signal has a desired clock frequency and to control the tuneable inductance such that its inductance value has a desired value for causing resonant or near-resonant transmission of the clock signal to the circuit block.

13. The integrated circuitry of claim 12 , wherein the tuneable clock source comprises a plurality of tuneable clock-signal generators, each configured to generate a clock signal having a clock frequency over its own frequency range, and circuitry for selecting and outputting the clock signal generated by one of those clock-signal generators.

Assignees

• Socionext Inc

Inventors

• Dedic Ian Juso
• Ahmed Abdullah Mohd Riazuddin

Classifications

• H03B27/00

  Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03B5/1293

  having means for achieving a desired tuning characteristic, e.g. linearising the frequency characteristic across the tuning voltage range · CPC title

• G06F3/05 Primary

  Digital input using the sampling of an analogue quantity at regular intervals of time {, input from a/d converter or output to d/a converter} · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title