Switched-capacitor buffer and related methods

Patent metadata

Field	Value
Publication number	US-10333394-B2
Application number	US-201615335956-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	May 13, 2016
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

First claim

What is claimed is:

1. A circuit, comprising:
a buffer configured to provide an output signal to a load in a first time period, in response to receiving an analog voltage, wherein the buffer comprises at least two transistors;
a capacitive element coupled to respective gate terminals of the at least two transistors, and configured to provide a DC signal to the respective gate terminals of the at least two transistors in the first time period, the capacitive element having a first terminal configured to be set to the analog voltage; and
a switch coupled between a DC reference voltage and the first terminal of the capacitive element and configured to set the first terminal of the capacitive element to the DC reference voltage in a second time period.

2. The circuit of claim 1 , wherein the switch is a first switch, and further comprising a second switch configured to couple the buffer to the load.

3. The circuit of claim 1 , wherein the switch is a first switch, and further comprising a second switch configured to couple the analog voltage to the buffer in the first time period.

4. The circuit of claim 3 , wherein the second time period and the first time period are non-overlapping.

5. The circuit of claim 1 , wherein the at least two transistors comprises a PMOS transistor and an NMOS transistor.

6. The circuit of claim 1 , further comprising control circuitry coupled to the switch and configured to place the switch in a conductive state in the second time period.

7. The circuit of claim 1 , wherein the load comprises an analog-to-digital converter.

8. The circuit of claim 1 , wherein the reference voltage is less than 1V.

9. A circuit, comprising:
an analog-to-digital converter;
a source-follower circuit coupled to the analog-to-digital converter and configured to drive the analog-to-digital converter with an analog voltage in a first time period, wherein the source-follower circuit comprises at least two transistors;
a capacitive element coupled to respective gate terminals of the at least two transistors, and configured to provide a DC signal to the respective gate terminals of the at least two transistors in the first time period, the capacitive element having a first terminal configured to be set to the analog voltage;
a switch coupled between a DC reference voltage and the first terminal of the capacitive element and configured to set the first terminal of the capacitive element to the DC reference voltage in a second time period.

10. The circuit of claim 9 , wherein the capacitive element is configured to bias the source-follower circuit in a linear region.

11. The circuit of claim 9 , wherein the switch is configured to charge the capacitive element to less than 1V.

12. The circuit of claim 9 , further comprising control circuitry coupled to the switch and configured to place the switch in a conductive state in the second time period.

13. The circuit of claim 9 , wherein the at least two transistors comprise a PMOS transistor and an NMOS transistor.

14. The circuit of claim 13 , wherein the NMOS transistor is a first NMOS transistor and the PMOS transistor is a first PMOS transistor, and further comprising a bias circuit coupled to the capacitive element, the bias circuit comprising a second PMOS transistor and a second NMOS transistor.

15. The circuit of claim 13 , wherein the NMOS transistor and the PMOS transistor are coupled to each other through respective source terminals.

16. The circuit of claim 9 , wherein the capacitive element is coupled between a first supply voltage and a second supply voltage, wherein the first and second supply voltages are different than zero and different from each other.

17. A method comprising:
in a first time period, setting a first terminal of a capacitive element to a DC reference voltage;
providing a DC signal to respective gate terminals of at least two transistors with the capacitive element;
in a second time period, setting the first terminal of the capacitive element to an analog voltage and providing the analog voltage to the at least two transistors; and
in response to receiving the DC signal and the analog voltage with the at least two transistors, driving a load during the second time period with an output signal.

18. The method of claim 17 , wherein driving the load comprises driving an analog-to-digital converter.

19. The method of claim 17 , wherein the first time period and the second time period are non-overlapping.

20. The method of claim 17 , wherein setting the first terminal of the capacitive element to the analog voltage comprises placing a switch in a conductive state in the first time period.

Assignees

• Mediatek Inc

Inventors

• Awad Ramy

Classifications

• H03F2200/252

  Multiple switches coupled in the input circuit of an amplifier are controlled by a circuit, e.g. feedback circuitry being controlling the switch · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03F2200/414

  A switch being coupled in the output circuit of an amplifier to switch the output on/off · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03F3/301

  CMOS common drain output SEPP amplifiers (H03F3/3008 takes precedence) · CPC title