Array substrate, color filter substrate, and manufacturing methods thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-10332913-B2
Application number	US-201414429952-A
Country	US
Kind code	B2
Filing date	May 7, 2014
Priority date	Nov 28, 2013
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

The invention discloses an array substrate, a color substrate, and manufacturing methods thereof, a display panel and a display device. The array substrate includes a plurality of gate lines and a plurality of data lines provided on a first base substrate to be intersected with each other, the gate lines and the data lines define a plurality of pixel units and at least part of the pixel units each provided therein with a first electrode, when the plurality of gate lines are sequentially scanned, the first electrode is loaded with a first voltage signal and a region corresponding to the first electrode is in a transparent state, and when the plurality of gate lines are reversely scanned, the first electrode is loaded with a second voltage signal, and a region corresponding to the first electrode is in a non-transparent state. The invention realizes a high switchover efficiency.

First claim

What is claimed is:

1. An array substrate, including: a plurality of gate lines and a plurality of data lines provided on a first base substrate to be intersected with each other, the plurality of gate lines and the plurality of data lines defining a plurality of pixel units, each of the pixel units is configured to display one color and is provided therein with a second electrode which is configured to drive a portion of the pixel unit corresponding thereto to display a color image, and at least one of the pixel units is further provided therein with a first electrode, the first electrode and the second electrode are formed in a same layer and in parallel to each other, wherein
when the plurality of gate lines are sequentially scanned, the first electrode is loaded with a first voltage signal, and a region corresponding to the first electrode is in a transparent state,
when the plurality of gate lines are reversely scanned, the first electrode is loaded with a second voltage signal, and a region corresponding to the first electrode is in a non-transparent state,
the at least one pixel unit provided therein with a first electrode is further provided with switch units, which include a first switch unit and a second switch unit, and wherein the first switch unit controls the first electrode to be loaded with the first or second voltage signal, and the second switch unit controls the second electrode to be loaded with a third or a fourth voltage signal, and wherein
the array substrate further comprises a plurality of common electrode lines, and the first switch unit includes a first switch tube, a gate of the first switch tube being connected with one corresponding gate line, a first terminal of the first switch tube being connected with one corresponding common electrode line and a second terminal of the first switch tube being connected with the first electrode, and
the second switch unit includes a second switch tube and a third switch tube, a gate of the second switch tube being connected with one corresponding gate line, a first terminal of the second switch tube being connected with one corresponding data line and a second terminal of the second switch tube being connected with the first electrode; and
a gate of the third switch tube being connected with one corresponding gate line, a first terminal of the third switch tube being connected with one corresponding data line and a second terminal of the third switch tube being connected with the second electrode.

2. The array substrate according to claim 1 , wherein
when the plurality of gate lines are sequentially scanned, the second electrode is loaded with the third voltage signal, and
when the plurality of gate lines are reversely scanned, the second electrode is loaded with the fourth voltage signal.

3. The array substrate according to claim 1 , wherein the first voltage signal, the third voltage signal and the fourth voltage signal are pixel voltage signals, and the second voltage signal is a common voltage signal.

4. The array substrate according to claim 1 , wherein the first terminal is a source electrode and the second terminal is a drain electrode.

5. The array substrate according to claim 1 , wherein the switch units and the first electrode are provided within each of the pixel units being apart from one another.

6. A display panel, including an array substrate and a color filter substrate provided opposite to each other, the array substrate according to claim 1 is adopted as the array substrate, wherein the color filter substrate includes light blocking strips provided on a second base substrate, the light block strips defining a plurality of pixel regions, each of the pixel regions being formed therein with a color matrix pattern, and at least part of the pixel regions each further provided therein with a transparent pattern, and the color filter substrate is adopted as the color filter substrate, the pixel unit of the array substrate is provided in correspondence with the pixel region of the color filter substrate, the first electrode of the array substrate is provided in correspondence with the transparent pattern of the color filter substrate and the second electrode of the array substrate is provided in correspondence with the color matrix pattern of the color filter substrate.

7. A display device, including the display panel according to claim 6 .

8. A display control method for the array substrate of claim 1 , comprising:
when the plurality of gate lines are sequentially scanned, the first electrode is loaded with the first voltage signal and a region corresponding to the first electrode is in a transparent state; and
when the plurality of the gate lines are reversely scanned, the first electrode is loaded with the second voltage signal and a region corresponding to the first electrode is in a non-transparent state.

9. A manufacturing method of an array substrate, including steps of:
S1, forming a plurality of gate lines and a plurality of data lines on a first base substrate to be intersected with each other so that the plurality of gate lines and the plurality of data lines define a plurality of pixel units, wherein each of the pixel units displays one color; and
S2, forming a second electrode in each of the pixel units on the first base substrate, and forming a first electrode in at least one of the pixel units on the first base substrate, wherein the first electrode is parallel to the second electrode and is used only for a transparent or non-transparent display, wherein
when the plurality of gate lines are sequentially scanned, the first electrode is loaded with a first voltage signal and a region corresponding to the first electrode is in a transparent state, and when the plurality of the gate lines are reversely scanned, the first electrode is loaded with a second voltage signal and a region corresponding to the first electrode is in a non-transparent state, wherein
the manufacturing method of an array substrate further comprising steps of:
providing a switch unit in the pixel unit provided therein with the first electrode, the switch unit including a first switch unit and a second switch unit, the first switch unit controls the first electrode to be loaded with the first or second voltage signal, and the second switch unit controls the second electrode to be loaded with the third or fourth voltage signal, and
forming a plurality of common electrode lines on the first base substrate, wherein
the first switch unit comprises a first switch tube, a gate of the first switch tube being connected with one corresponding gate line, a first terminal of the first switch tube being connected with one corresponding common electrode line and a second terminal of the first switch tube being connected with the first electrode, and the second switch unit includes a second switch tube and a third switch tube, a gate of the second switch tube being connected with one corresponding gate line, a first terminal of the second switch tube being connected with one corresponding data line and a second terminal of the second switch tube being connected with the first electrode; and
a gate of the third switch tube being connected with one corresponding gate line, a first terminal of the third switch tube being connected with one corresponding data line and a second terminal of the third switch tube being connected with the second electrode.

10. The manufacturing method according to claim 9 , wherein
when the plurality of gate lines are sequentially scanned, the second electrode is loaded with a third voltage, and
when the plurality of gate lines are reversely scanned, the second electrode is loaded with a fourth voltage.

11. The manufa

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Chen Huabin
• Yuan Jianfeng

Classifications

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02B5/201

  in the form of arrays · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title