Semiconductor device package and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10332851-B2
Application number	US-201715630843-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Jun 22, 2017
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a first carrier including a power output;
a second carrier disposed on the first carrier and having a first surface and including a power layer adjacent to the first surface of the second carrier;
an electrical component disposed on the first surface of the second carrier and electrically connected to the power layer;
a conductive element disposed on the first surface of the second carrier and electrically connected to the power layer; and
a connection structure including a first terminal and a second terminal, wherein the first terminal of the connection structure is connected to the power output and the second terminal of the connection structure is connected to the conductive element.

2. The semiconductor device package claim 1 , wherein the power layer includes a first portion and a second portion separated from the first portion.

3. The semiconductor device package claim 2 , wherein the electrical component has an active surface and includes a plurality of pads disposed on the active surface, and wherein a first pad of the plurality of pads contacts the first portion of the power layer and a second pad of the plurality of pads contacts the second portion of the power layer.

4. The semiconductor device package of claim 2 , wherein the conductive element includes a first portion, a second portion, and a third portion, and wherein the first portion of the conductive element contacts the first portion of the power layer and the second portion of the conductive element contacts the second portion of the power layer.

5. The semiconductor device package of claim 4 , further comprising a package body encapsulating the first surface of the second carrier, the conductive element, and the electrical component, wherein the third portion of the conductive element is exposed from the package body.

6. The semiconductor device package of claim 5 , further comprising a heat spreader disposed on the package body and connected to the conductive element.

7. The semiconductor device package of claim 2 , further comprising an insulating layer disposed on the first surface of the second carrier,
wherein the first portion of the power layer is partially exposed from the insulating layer,
wherein the conductive element includes a first portion, a second portion extending over the electrical component, and a third portion, and
wherein the first portion of the conductive element contacts the first portion of the power layer and the third portion of the conductive element contacts the insulating layer.

8. The semiconductor device package claim 1 , wherein the conductive element includes an extension portion extending over the electrical component.

9. The semiconductor device package of claim 1 , further comprising a package body encapsulating the first surface of the second carrier, the conductive element, and the electrical component, wherein at least one surface of the conductive element is exposed from the package body.

10. The semiconductor device package of claim 9 , further comprising a heat spreader disposed on the package body and connected to the conductive element.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yang Chung-Chieh
• Wang Sheng-Ming
• Chen Tien-Szu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title