Semiconductor device, and display device and electronic device having the same

Patent metadata

Field	Value
Publication number	US-10325932-B2
Application number	US-201615222378-A
Country	US
Kind code	B2
Filing date	Jul 28, 2016
Priority date	Jan 7, 2006
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first transistor comprising a gate terminal, a first terminal, and a second terminal;
a second transistor comprising a gate terminal, a first terminal, and a second terminal;
a third transistor comprising a gate terminal, a first terminal, and a second terminal;
a fourth transistor comprising a gate terminal, a first terminal, and a second terminal;
a fifth transistor comprising a gate terminal, a first terminal, and a second terminal;
a sixth transistor comprising a gate terminal, a first terminal, and a second terminal;
a seventh transistor comprising a gate terminal, a first terminal, and a second terminal; and
an eighth transistor comprising a gate terminal, a first terminal, and a second terminal;
wherein the first terminal of the first transistor is electrically connected to the gate terminal of the second transistor, the first terminal of the fourth transistor, the gate terminal of the fifth transistor, and the first terminal of the seventh transistor,
wherein the first terminal of the second transistor is electrically connected to the first terminal of the third transistor and an output terminal,
wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the fourth transistor, and the first terminal of the eighth transistor,
wherein the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor, and the gate terminal of the eighth transistor,
wherein the gate terminal of the sixth transistor is electrically connected to the second terminal of the sixth transistor, and
wherein the second terminal of the eighth transistor is electrically connected to a wiring configured to be supplied with a control signal.

2. The semiconductor device according to claim 1 , wherein the second terminal of the first transistor is electrically connected to a first power supply.

3. The semiconductor device according to claim 1 , wherein the gate terminal of the sixth transistor and the second terminal of the sixth transistor is electrically connected to a first power supply.

4. The semiconductor device according to claim 1 , wherein the second terminal of the eighth transistor is electrically connected to an input terminal.

5. The semiconductor device according to claim 1 , wherein the second terminal of the second transistor is electrically connected to an input terminal.

6. The semiconductor device according to claim 1 , wherein the second terminal of the seventh transistor is electrically connected to a second power supply.

7. The semiconductor device according to claim 1 , wherein the output terminal is electrically connected to a buffer circuit.

8. A semiconductor device comprising:
a first transistor comprising a gate terminal, a first terminal, and a second terminal;
a second transistor comprising a gate terminal, a first terminal, and a second terminal;
a third transistor comprising a gate terminal, a first terminal, and a second terminal;
a fourth transistor comprising a gate terminal, a first terminal, and a second terminal;
a fifth transistor comprising a gate terminal, a first terminal, and a second terminal;
a sixth transistor comprising a gate terminal, a first terminal, and a second terminal;
a seventh transistor comprising a gate terminal, a first terminal, and a second terminal;
an eighth transistor comprising a gate terminal, a first terminal, and a second terminal; and
a capacitor comprising a first electrode and a second electrode,
wherein the first terminal of the first transistor is electrically connected to the gate terminal of the second transistor, the first terminal of the fourth transistor, the gate terminal of the fifth transistor, the first terminal of the seventh transistor, and the first electrode of the capacitor,
wherein the first terminal of the second transistor is electrically connected to the first terminal of the third transistor the second electrode of the capacitor, and an output terminal,
wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the fourth transistor, and the first terminal of the eighth transistor,
wherein the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor, and the gate terminal of the eighth transistor,
wherein the gate terminal of the sixth transistor is electrically connected to the second terminal of the sixth transistor, and
wherein the second terminal of the eighth transistor is electrically connected to a wiring configured to be supplied with a control signal.

9. The semiconductor device according to claim 8 , wherein the second terminal of the first transistor is electrically connected to a first power supply.

10. The semiconductor device according to claim 8 , wherein the gate terminal of the sixth transistor and the second terminal of the sixth transistor is electrically connected to a first power supply.

11. The semiconductor device according to claim 8 , wherein the second terminal of the eighth transistor is electrically connected to an input terminal.

12. The semiconductor device according to claim 8 , wherein the second terminal of the second transistor is electrically connected to an input terminal.

13. The semiconductor device according to claim 8 , wherein the second terminal of the seventh transistor is electrically connected to a second power supply.

14. The semiconductor device according to claim 8 , wherein the output terminal is electrically connected to a buffer circuit.

15. A semiconductor device comprising:
a first flip-flop circuit, a second flip-flop circuit, and a third flip-flop circuit each comprising:
a first transistor comprising a gate terminal, a first terminal, and a second terminal;
a second transistor comprising a gate terminal, a first terminal, and a second terminal;
a third transistor comprising a gate terminal, a first terminal, and a second terminal;
a fourth transistor comprising a gate terminal, a first terminal, and a second terminal;
a fifth transistor comprising a gate terminal, a first terminal, and a second terminal;
a sixth transistor comprising a gate terminal, a first terminal, and a second terminal;
a seventh transistor comprising a gate terminal, a first terminal, and a second terminal;
an eighth transistor comprising a gate terminal, a first terminal, and a second terminal; and
a capacitor comprising a first electrode and a second electrode,
wherein the first terminal of the first transistor is electrically connected to the gate terminal of the second transistor, the first terminal of the fourth transistor, the gate terminal of the fifth transistor, the first terminal of the seventh transistor, and the first electrode of the capacitor,
wherein the first terminal of the second transistor is electrically connected to the first terminal of the third transistor, the second electrode of the capacitor, and an output terminal,
wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the fourth transistor, and the first terminal of the eighth transistor,
wherein the first terminal of the fifth transistor is electrically connected to the first terminal of the sixth transistor, and the gate terminal of the eighth transistor, and
wherein the gate terminal of the sixth transistor is electrically connected to the second terminal of the sixth transistor;
wherein the gate of the first transistor in the second flip-flop circuit is electrically connected to the output termina

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title