Two-dimensional array of CMOS control elements

Patent metadata

Field	Value
Publication number	US-10325915-B2
Application number	US-201615294186-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	May 4, 2016
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes semiconductor devices. The plurality of CMOS control elements each including a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device and an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device. The plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

First claim

What is claimed is:

1. An electronic device comprising:
a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising semiconductor devices, the plurality of CMOS control elements each comprising:
a PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device; and
an NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device, wherein the PMOS semiconductor device portion and the NMOS semiconductor device portion are separated by a separation distance; and

a plurality of MEMS devices arranged in a two-dimensional array, each MEMS device of the plurality of MEMS devices associated with a CMOS control element of the plurality of CMOS control elements;
wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the plurality of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the plurality of CMOS control elements.

2. The electronic device of claim 1 , wherein the plurality of MEMS devices comprise a plurality of ultrasonic transducers.

3. The electronic device of claim 2 , wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

4. The electronic device of claim 2 further comprising:
an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a semiconductor device of the PMOS semiconductor device portion and to a semiconductor device of the NMOS semiconductor device portion.

5. The electronic device of claim 4 , wherein the electrical connections are for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion.

6. The electronic device of claim 1 , wherein the two-dimensional array comprises a plurality of rows of CMOS control elements, wherein adjacent rows have an alternating orientation of the CMOS control elements, such that CMOS control elements of a first row have reflectional symmetry with CMOS control elements of a second row of relative to an adjacent edge of the first row and the second row.

7. The electronic device of claim 1 , wherein CMOS control elements have reflectional symmetry with adjacent CMOS control elements relative to adjacent edges.

8. An electronic device comprising:
a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising a semiconductor device, the plurality of CMOS control elements comprising:
a first subset of CMOS control elements comprising a PMOS semiconductor device portion, the PMOS semiconductor device portion comprising a high voltage PMOS device and a low voltage PMOS device;
a second subset of CMOS control elements comprising an NMOS semiconductor device portion, the NMOS semiconductor device portion comprising a high voltage NMOS device and a low voltage NMOS device; and

a plurality of MEMS devices arranged in a two-dimensional array, each MEMS device of the plurality of MEMS devices associated with a CMOS control element of the plurality of CMOS control elements;
wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that the PMOS semiconductor device portion of a CMOS control element of the first subset of CMOS control elements is only adjacent to other PMOS semiconductor device portions of adjacent CMOS control elements of the first subset of CMOS control elements, and such that the NMOS semiconductor device portion of a CMOS control element of the second subset of CMOS control elements is only adjacent to other NMOS semiconductor device portions of adjacent CMOS control elements of the second subset of CMOS control elements.

9. The electronic device of claim 8 , wherein the plurality of MEMS devices comprise a plurality of ultrasonic transducers.

10. The electronic device of claim 9 , wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

11. The electronic device of claim 9 further comprising:
an interconnect layer disposed between the plurality of CMOS control elements and the plurality of ultrasonic transducers, the interconnect layer comprising electrical connections for interconnecting each ultrasonic transducer to a semiconductor device of the PMOS semiconductor device portion and to a semiconductor device of the NMOS semiconductor device portion.

12. The electronic device of claim 11 , wherein the electrical connections are for interconnecting each ultrasonic transducer to a high voltage PMOS device and a low voltage PMOS device of the PMOS semiconductor device portion and to a high voltage NMOS device and a low voltage NMOS device of the NMOS semiconductor device portion.

13. The electronic device of claim 8 , wherein the two-dimensional array comprises a plurality of rows comprising:
a first row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the PMOS semiconductor device portion are adjacent to a first edge of the first row of the CMOS control elements, wherein the first edge of the first row and a second edge of the first row are opposite edges of the CMOS control elements of the first row;
a second row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the NMOS semiconductor device portion are adjacent to a first edge of the second row of the CMOS control elements, wherein the first edge of the second row and a second edge of the second row are opposite edges of the CMOS control elements of the second row, and wherein the second edge of the second row is adjacent to the second edge of the first row;
a third row comprising CMOS control elements of the second subset of CMOS control elements, wherein the semiconductor devices of the NMOS semiconductor device portion are adjacent to a first edge of the third row of the CMOS control elements, wherein the first edge of the third row and a second edge of the third row are opposite edges of the CMOS control elements of the third row, and wherein the first edge of the third row is adjacent to the first edge of the second row; and
a fourth row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the PMOS semiconductor device portion are adjacent to a first edge of the fourth row of the CMOS control elements, wherein the first edge of the fourth row and a second edge of the fourth row are opposite edges of the CMOS control elements of the fourth row, and wherein the second edge of the fourth row is adjacent to the second edge of the third row.

14. The electronic device of claim 13 , wherein the plurality of rows further comprises:
a fifth row comprising CMOS control elements of the first subset of CMOS control elements, wherein the semiconductor devices of the

Assignees

• Invensense Inc

Inventors

• Salvia James Christian
• Perrott Michael H
• Voros Marian
• NG Eldwin
• Tsai Julius Ming-Lin
• Apte Nikhil

Classifications

• G06F2203/0338

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• B81C1/00246

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• B06B1/0622

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• H01L27/0922

  Electricity · mapped topic