Methods, apparatus and system for threshold voltage control in FinFET devices

Patent metadata

Field	Value
Publication number	US-10325824-B2
Application number	US-201715622061-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Jun 13, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

First claim

What is claimed is:

1. A method, comprising:
determining a first threshold voltage of a first transistor gate comprising a first gate channel having a first length;
determining a second length of a second gate channel of a second transistor gate;
determining a process adjustment of said second gate based on said second length for providing a second threshold voltage of said second transistor gate, wherein said second threshold voltage is within a predetermined range of said first threshold voltage, wherein determining said process adjustment comprises determining a thickness of a first work function metal (WFM) layer of said first transistor gate and determining a thickness of a second WFM of said second transistor gate, wherein said second WFM layer is thicker than the thickness of said first WFM layer, in response to a determination that said first threshold voltage is at least one of a PFET low voltage threshold (PLVT), a PFET regular voltage threshold (PRVT), a PFET super-low voltage threshold (PSLVT), an NFET low voltage threshold (NLVT), a NFET regular voltage threshold (NRVT), or a NFET super-low voltage threshold (NSLVT); and
providing data relating to process adjustment to a process controller for performing said process adjustment.

2. The method of claim 1 , wherein determining said first voltage threshold comprises determining whether said first transistor gate is one of a PFET low voltage threshold (PLVT), a PFET regular voltage threshold (PRVT), a PFET super-low voltage threshold (PSLVT), an NFET low voltage threshold (NLVT), a NFET regular voltage threshold (NRVT), or a NFET super-low voltage threshold (NSLVT).

3. The method of claim 2 , wherein:
said PLVT and said NLVT are an absolute value of about 0.20 Volts;
said PRVT and said NRVT are an absolute value of about 0.25 Volts; and
said PSLVT and said NSLVT are an absolute value of about 0.15 Volts.

4. The method of claim 1 , wherein a first WFM of said first transistor gate is of an opposite polarity of a second WFM.

5. The method of claim 1 , wherein determining said process adjustment comprises determining a first material for said first WFM and a second material for said second WFM.

6. The method of claim 1 , wherein determining said process adjustment comprises adjusting a halo layer adjacent a source and drain region corresponding to said second transistor gate, wherein adjusting said halo layer comprises providing a thinner halo layer or eliminating said halo layer.

7. The method of claim 4 , wherein determining a thickness of a second WFM comprises determining that the second WFM layer is to be in the range of about 40-50 Å.

8. A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device comprising at least one fin field effect transistor (finFET); and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system;
wherein said semiconductor device processing system is adapted to:
determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length;
determine a second length of a second gate channel of a second transistor gate;
determine a process adjustment of said second gate based on said second length for providing a second threshold voltage of said second transistor gate, wherein said second threshold voltage is within a predetermined range of said first threshold voltage, wherein determining said process adjustment comprises determining a thickness of a first work function metal (WFM) layer of said first transistor gate and determining a thickness of a second WFM of said second transistor gate, wherein said second WFM layer is thicker than the thickness of said first WFM layer, in response to a determination that said first threshold voltage is at least one of a PFET low voltage threshold (PLVT), a PFET regular voltage threshold (PRVT), a PFET super-low voltage threshold (PSLVT), an NFET low voltage threshold (NLVT), a NFET regular voltage threshold (NRVT), or a NFET super-low voltage threshold (NSLVT); and
provide data relating to process adjustment to said processing controller for performing said process adjustment.

9. The system of claim 8 , further comprising a design unit configured to generate a first design comprising a definition for a process mask, a definition for forming said first and second transistor gates, wherein data from said design unit is used by said processing controller to control an operation of said semiconductor device processing system.

10. The system of claim 8 , wherein said semiconductor device processing system is further adapted to:
adjust a halo layer adjacent a source and drain region corresponding to said second transistor gate, wherein adjusting said halo layer comprises providing a thinner halo layer or eliminating said halo layer; and
determine a third threshold voltage of a first gate-source-drain design and a fourth threshold voltage of a second gate-drain-source design and determine the thickness of a WFM layer of said second gate-drain-source design for causing said fourth threshold voltage to be within a predetermined range of said third threshold voltage.

Assignees

• Globalfoundries Inc

Inventors

• Togo Mitsuhiro
• Asra Ram
• Zhang Xing
• Balasubramaniam Palanivel

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• H01L27/0922

  Electricity · mapped topic

• H01L21/82385

  Electricity · mapped topic