Flexible control systems and methods for device arrays

Patent metadata

Field	Value
Publication number	US-10325727-B2
Application number	US-201815898193-A
Country	US
Kind code	B2
Filing date	Feb 15, 2018
Priority date	Feb 15, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

The present subject matter relates to devices, systems, and methods for controlling an array of two-state elements that can be independently positioned in either first state or a second state. A non-volatile memory in communication with the plurality of two-state elements is configured to receive an input digital control word that addresses a location within the non-volatile memory and to output one of a plurality of array control words stored at the location addressed within the memory to the plurality of two-state elements, wherein the array control word sets a predetermined combination of the plurality of two-state elements to be in the first state and in the second state, and wherein the predetermined combination of the plurality of two-state elements in the first state and in the second state optimally achieves a desired behavior of the array corresponding to the input digital control word.

First claim

What is claimed is:

1. A method for controlling an array of two-state elements that can be independently positioned in either a first state or a second state, the method comprising:
programming a non-volatile memory, wherein programming the non-volatile memory comprises:
measuring a device response in the first state and in the second state for each element in the array of two-state elements; and
for each of a plurality of input digital control words, storing one of a plurality of array control words that sets a state of each element in the array of two-state elements to optimally achieve a desired total combined activity of the array of two-state elements;

receiving an input digital control word corresponding to the desired total combined activity of the array of two-state elements;
addressing a location within the non-volatile memory based on the input digital control word, wherein the location stores the one of the plurality of array control words corresponding to a predetermined combination of the two-state elements in a first state and in a second state; and
applying the one of the plurality of array control words to the array of two-state elements to control the array to set the predetermined combination of the two-state elements to be in the first state and in the second state, wherein the predetermined combination of the two-state elements in the first state and in the second state optimally achieves the desired total combined activity of the array of two-state elements.

2. The method of claim 1 , wherein receiving the input digital control word comprises receiving a serial digital control word.

3. The method of claim 1 , wherein receiving the input digital control word comprises receiving a parallel digital control word.

4. The method of claim 1 , wherein the non-volatile memory comprises a one-time programmable memory.

5. The method of claim 1 , wherein addressing a location within the non-volatile memory comprises addressing one of a plurality of locations in the memory that are each associated with the desired total combined activity of the array of two-state elements, wherein different array control words corresponding to different states of the elements in the array are stored at the plurality of locations.

6. The method of claim 1 , wherein programming the non-volatile memory comprises providing multiple different sets of array control words that provide different array behavior corresponding to multiple different sets of input digital control words; and
wherein receiving the input digital control word comprises receiving additional address bits that identify one of the multiple different sets of array control words.

7. The method of claim 6 , wherein the multiple different sets of array control words define multiple different tuning curves.

8. The method of claim 6 , wherein the multiple different sets of array control words address discrete sub-arrays within the array of two-state elements.

9. The method of claim 1 , wherein the two-state elements comprise tunable capacitors that are each switchable between a maximum capacitance in the first state and a minimum capacitance in the second state; and
wherein the desired behavior of the array of two-state elements comprises a desired total array capacitance.

10. A tunable component comprising:
a plurality of two-state elements arranged in a functional array, wherein each of the two-state elements can be independently positioned in either a first state or a second state; and
a non-volatile memory in communication with the plurality of two-state elements, wherein the non-volatile memory is configured to receive an input digital control word that addresses a location within the non-volatile memory and to output one array control word of a plurality of array control words stored at the location addressed within the memory to the plurality of two-state elements;
wherein the one array control word sets a predetermined combination of the plurality of two-state elements to be in the first state and in the second state, wherein the predetermined combination of the plurality of two-state elements in the first state and in the second state optimally achieves a total combined activity of the array corresponding to the input digital control word; and
wherein, for each of the plurality of array control words, the predetermined combination of the plurality of two-state elements to be in the first state and in the second state is selected based at least partially on a measured device response in the first state and in the second state for each element in the plurality of two-state elements.

11. The tunable component of claim 10 , wherein the plurality of two-state elements comprises a plurality of RF switches.

12. The tunable component of claim 10 , wherein the plurality of two-state elements comprises a plurality of RF-MEMS capacitors.

13. The tunable component of claim 10 , wherein the non-volatile memory and the plurality of elements are on a common substrate.

Assignees

• Wispry Inc

Inventors

• Morris Iii Arthur S
• Masse Christophe
• Maimone Peter
• Mckillop John Slaton

Classifications

• H01G5/16

  using variation of distance between electrodes · CPC title

• H01G5/38 Primary

  Multiple capacitors, e.g. ganged · CPC title

• H01G7/00

  Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title