Memory system having impedance calibration circuit

Patent metadata

Field	Value
Publication number	US-10325671-B2
Application number	US-201815970242-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	Sep 11, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A memory system includes: a buffer memory device including a reference voltage pad; a memory controller including a controller ZQ pad; and a controller calibration resistor, wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other.

First claim

What is claimed is:

1. A memory system comprising:
a buffer memory device including a reference voltage pad;
a memory controller including a controller ZQ pad; and
a controller calibration resistor,
wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other,
wherein the memory controller includes a reference voltage generating unit configured to generate a reference voltage,
wherein the memory controller includes a comparator that has a first input and a second input, and
wherein the first input is coupled to the controller ZQ pad, and the reference voltage is input to the second input.

2. The memory system of claim 1 ,
wherein, when an impedance calibration operation is activated, a voltage output to the controller ZQ pad is substantially equal to the reference voltage.

3. The memory system of claim 2 , wherein the memory controller includes a pull-up resistor unit coupled to the controller ZQ pad,
wherein, when the impedance calibration operation is activated, the pull-up resistor unit is configured to change the resistance of a pull-up resistor, based on the resistance of the controller calibration resistor and the reference voltage.

4. The memory system of claim 3 , wherein the pull-up resistor unit includes a plurality of transistors coupled in parallel to each other,
wherein the widths of the plurality of transistors are configured in a binary relationship.

5. The memory system of claim 3 , wherein the memory controller includes a pull-up counter configured to generate a pull-up code,
wherein the pull-up counter generates the pull-up code that adjusts the resistance of the pull-up resistor of the pull-up resistor unit in synchronization with a clock signal.

6. The memory system of claim 3 , wherein, when an input/output power voltage is applied, the memory controller performs the impedance calibration operation in real time.

7. The memory system of claim 2 , wherein an input/output power voltage of the memory controller is approximately two times greater than the reference voltage.

8. The memory system of claim 2 , wherein the buffer memory device determines whether a data signal is logic ‘high’ or logic ‘low’ in a data input operation.

9. The memory system of claim 8 , further comprising a memory calibration resistor coupled to the buffer memory device,
wherein the memory calibration resistor has a resistance substantially equal to that of the controller calibration resistor.

10. The memory system of claim 8 , wherein the buffer memory device includes a plurality of dynamic random access memories (DRAMs),
wherein the plurality of DRAMs share a data transmission line for exchanging data with the memory controller.

11. The memory system of claim 1 , wherein the memory controller includes a pull-up counter configured to generate a pull-up code,
wherein the pull-up counter adjusts the pull-up code in synchronization with a clock signal, based on an output voltage of the comparator.

12. A memory system comprising:
a buffer memory device;
a memory controller including a first pad;
a controller calibration resistor coupled to the memory controller through the first pad; and
a memory calibration resistor coupled to the buffer memory device through a second pad,
wherein the memory controller performs an impedance calibration operation, based on the resistance of the controller calibration resistor,
wherein the buffer memory device determines whether a data signal is logic ‘high’ or logic ‘low’ in a data input operation, based on a voltage output from the memory controller through the first pad, and
wherein the buffer memory device autonomously performs an impedance calibration operation, based on the resistance of the memory calibration resistor.

13. The memory system of claim 12 , wherein the buffer memory device includes a third pad,
wherein the buffer memory device receives, through the third pad, the voltage output through the first pad.

14. The memory system of claim 12 , wherein the memory controller includes a reference voltage generating unit configured to generate a reference voltage,
wherein, when the impedance calibration operation is activated, the voltage output through the first pad is substantially equal to the reference voltage.

15. The memory system of claim 14 , wherein the memory controller includes an impedance calibration circuit coupled to the first pad,
wherein the impedance calibration circuit is configured to change the voltage output through the first pad, based on the resistance of the controller calibration resistor and the reference voltage.

16. The memory system of claim 12 , wherein, when an input/output power voltage is applied, the memory controller performs the impedance calibration operation in real time.

17. The memory system of claim 12 , wherein the buffer memory device includes a double data rate fourth-generation synchronous dynamic random access memory (DDR4 SDRAM).

18. The memory system of claim 12 , wherein the buffer memory device includes a plurality of DRAMs,
wherein the plurality of DRAMs share a data transmission line for exchanging data with the memory controller.

19. A transmission system comprising:
first and second devices; and
a transmission line suitable for transferring a signal between the first and second devices,
wherein the first device matches impedances between the first device and the transmission line with reference to a first calibration resistance, and
wherein the second device matches impedances between the second device and the transmission line with reference to a second calibration resistance and the voltage of the first calibration resistance when the first device completes the impedance matching.

Assignees

• Sk Hynix Inc

Inventors

• Kim Hee Jun
• Hwang Minsoon

Classifications

• G11C29/50008 Primary

  of impedance · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G06F13/4086 Primary

  Bus impedance matching, e.g. termination · CPC title