Scalable architecture for analog matrix operations with resistive devices

Patent metadata

Field	Value
Publication number	US-10325006-B2
Application number	US-201514868496-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 29, 2015
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

In some aspects, a method for performing analog matrix inversion on a matrix with a network of resistive device arrays B, W, Q, and C is described. The method may include initializing arrays W, Q, B and C, updating the connections of array W in parallel and array Q in parallel until a predetermined condition is satisfied, and responsive to determining that the predetermined condition is satisfied, outputting an inverted matrix based on outputs from the connections of arrays B, W, Q, and C.

First claim

The invention claimed is:

1. A system for performing analog matrix inversion on a matrix, the system comprising:
a network of resistive device arrays B, W, Q, and C, wherein each of the arrays comprises a plurality of connections, each connection comprising a resistive device configured to store a value, the network configured to:
initialize arrays W, Q, B and C;
update the plurality of connections of array Win parallel and Q in parallel until a predetermined condition is satisfied; and
responsive to determining that the predetermined condition is satisfied, output an inverted matrix based on outputs from the connections of arrays B, W, Q, and C.

2. The system of claim 1 , wherein the predetermined condition is i=n, where n is a value corresponding to a size of the matrix.

3. The system of claim 1 , wherein,
array B comprises x connections and z connections;
array W comprises y connections and the z connections;
array Q comprises the z connections and ζ connections; and
array C comprises the x connections and y* connections.

4. The system of claim 3 , wherein the updates to the plurality of connections of arrays B, W, Q, and C causes the network to:
read with the outputs of the arrays B, W, Q, and C, that are responsive to the initialization from the x connections, y* connections, and the z connections;
pulse a first voltage pulse into the x connections;
read a z term from the z connections and a y* term from the y* connections, wherein the z and y terms are responsive to the first voltage pulse;
pulse a second voltage pulse into the z connections;
read, using a CMOS circuit, a y term from y connections, a y* term from the y* connections, and a ζ term from the ζ connections, wherein the y, y* and ζ terms are responsive to the first and second voltage pulses;
compute a value ε based on y and the y* terms; and
compute a value η using the ζ terms.

5. The system of claim 3 , wherein the ζ connections are also an output of matrix Q.

6. The system of claim 1 , wherein the resistive device arrays are 2D cross-point devices comprised of resistive devices functioning as weighted connections between neurons.

7. A non-transitory computer-readable storage medium storing instructions executable by a processor to perform a method for performing analog matrix inversion on a matrix with a network of resistive device arrays B, W, Q, and C, the method comprising:
initializing arrays W, Q, B and C, wherein each of the arrays comprises a plurality of connections, each connection comprising a resistive device configured to store a value;
updating the connections of arrays Win parallel and Q in parallel, until a predetermined condition is satisfied; and
responsive to determining that a predetermined condition is satisfied, outputting an inverted matrix based on outputs from the connections of arrays B, W, Q, and C.

8. The computer-readable storage medium of claim 7 , wherein the predetermined condition is i=n, where n is a value corresponding to a size of the matrix.

9. The computer-readable storage medium of claim 7 , wherein,
array B comprises x connections and z connections;
array W comprises y connections and the z connections;
array Q comprises the z connections and connections; and
array C comprises the x connections and y* connections.

10. The computer-readable storage medium of claim 9 , wherein updating the connections of arrays B, W, Q, and C comprises:
reading, with the outputs of the arrays B, W, Q, and C, that are responsive to the initialization from the x connections, the y* connections, and the z connections;
pulsing a first voltage pulse into the x connections;
reading a z term from the z connections and a y* term from the y* connections, wherein the z and y terms are responsive to the first voltage pulse;
pulsing a second voltage pulse into the z connections;
reading, using a CMOS circuit, a y term from the y connections, a y* term from the y* connections, and a ζ term from the ζ connections, wherein the y, y* and ζ terms are responsive to the first and second voltage pulses;
computing a value ε based on y and the y* terms; and
computing a value η using the ζ terms.

11. The computer-readable storage medium of claim 9 , wherein the ζ connections are also an output of matrix Q.

12. The computer-readable storage medium of claim 7 , wherein the resistive device arrays are 2D cross-point devices comprised of resistive devices functioning as weighted connections between neurons.

Assignees

• Int Business Machines Int
• IBM

Inventors

• Gokmen Tayfun
• Kim Seyoung

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/0635

  Physics · mapped topic