Systems and devices having a scalable basic input/output system (BIOS) footprint and associated methods

Patent metadata

Field	Value
Publication number	US-10324867-B2
Application number	US-201715482646-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 7, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

First claim

The invention claimed is:

1. An electronic device, comprising:
a processor; and
a non-volatile memory (NVM) device communicatively coupled to the processor, the NVM device including a basic input/output system (BIOS) image and instructions that, when executed on the processor, establish a system address space comprising:
a system memory low region;
a memory-mapped input/output (MMIO) low region above the system memory low region;
a system memory high region above the MMIO low region;
a MMIO high region above the system memory high region;
a BIOS region in the MMIO low region adjacent the system memory high region;
an input/output (I/O) advanced programmable interrupt controller (APIC) region in the MMIO low region below the BIOS region; and
a scalable extended BIOS (eBIOS) region in either the MMIO low region below the I/O APIC region or the MMIO high region.

2. The device of claim 1 , wherein the eBIOS region is at least 32 MB in size.

3. The device of claim 2 , wherein the processor is in a processor package, a multi-core processor package, a system-on-chip package (SoC), a system-in-package (SiP) package, system-on-package (SoP) package, or a combination thereof.

4. The device of claim 1 , wherein the NVM device is flash memory.

5. The device of claim 1 , wherein the NVM device is three dimensional (3D) cross point memory.

6. A computing system, comprising:
a processor;
an input/output hub (IOH) communicatively coupled to the processor; and
a non-volatile memory (NVM) device communicatively coupled to the IOH, the NVM device including a basic input/output system (BIOS) image and instructions that, when executed on the processor, establish a system address space comprising:
a system memory low region;
a memory-mapped input/output (MMIO) low region above the system memory low region;
a system memory high region above the MMIO low region;
a MMIO high region above the system memory high region;
a BIOS region in the MMIO low region adjacent the system memory high region;
an input/output (I/O) advanced programmable interrupt controller (APIC) region in the MMIO low region below the BIOS region; and
a scalable extended BIOS (eBIOS) region in either the MMIO low region below the I/O APIC region or the MMIO high region.

7. The system of claim 6 , wherein the extended BIOS region is at least 32 MB in size.

8. The system of claim 6 , wherein the processor can include one or more processors, one or more processor cores, or a combination thereof.

9. The system of claim 8 , wherein the processor is in a processor package, a multi-core processor package, a system-on-chip package (SoC), a system-in-package (SiP) package, system-on-package (SoP) package, or a combination thereof.

10. The system of claim 6 , wherein the NVM device is flash memory.

11. The system of claim 6 , wherein the NVM device is three dimensional (3D) cross point memory.

12. The system of claim 6 , further comprising:
a NVM BIOS controller communicatively coupled to the IOH and to the NVM device; and
wherein the IOH further comprises circuitry configured to:
identify MMIO access requests to either the BIOS region or the eBIOS region from the processor; and
send the BIOS region and the eBIOS region MMIO access requests to the NVM BIOS controller.

13. The system of claim 12 , wherein the NVM BIOS controller further comprises circuitry configured to:
determine physical addresses from linear addresses for each of the BIOS region and the eBIOS region MMIO access requests;
generate BIOS access commands for each MMIO access request;
send the BIOS access commands for each BIOS region MMIO access request to a BIOS image region of the NVM device at the associated physical address; and
send the BIOS access commands for each eBIOS region MMIO access request to an eBIOS image region of the NVM device at the associated physical address.

14. The system of claim 13 , wherein the NVM BIOS controller further comprises circuitry further configured to:
determine the physical addresses from linear addresses for each of the BIOS region and the eBIOS region MMIO access requests, the circuitry is further configured to determine a first physical address and a second physical address from each linear address;
send the BIOS access commands for each BIOS region MMIO access request to the BIOS image region, the circuitry is further configured to send each BIOS access command to a first BIOS image region at the associated first physical address and to a second BIOS image region at the associated second physical address; and
send the BIOS access commands for each eBIOS region MMIO access request to the eBIOS image region, the circuitry is further configured to send each BIOS access command to a first eBIOS image region at the associated first physical address and to a second eBIOS image region at the associated second physical address.

15. The system of claim 12 , wherein the NVM BIOS controller is a serial peripheral interface (SPI) controller.

16. A method for scalably extending a basic input/output system (BIOS) region size in a system address space, comprising:
establishing, by executing BIOS instructions on a processor, a system address space comprising:
a system memory low region;
a memory-mapped input/output (MMIO) low region above the system memory low region;
a system memory high region above the MMIO low region;
a MMIO high region above the system memory high region;
a BIOS region in the MMIO low region adjacent the system memory high region;
an input/output (I/O) advanced programmable interrupt controller (APIC) region in the MMIO low region below the BIOS region; and
a scalable extended BIOS (eBIOS) region in either the MMIO low region below the I/O APIC region or the MMIO high region.

17. The method of claim 16 , wherein, upon a system reboot, establishing the eBIOS region of the system address space further comprises:
reading, by the processor, basic BIOS instructions from a reset vector in a BIOS image, wherein the BIOS image is stored in a non-volatile memory (NVM) device;
sending first instructions from the processor to a NVM BIOS controller to load a basic BIOS portion of the BIOS image from the NVM device into the BIOS region of the system address space;
executing, by the processor, instructions from the BIOS image to initialize an eBIOS configuration register that includes an eBIOS address range and an enable/disable switch;
programming, by the processor to an I/O hub (IOH) and the NVM BIOS controller, the eBIOS address range;
mapping, by the NVM BIOS controller, the eBIOS region to the system address space at the eBIOS address range;
mapping, by the NVM BIOS controller, the eBIOS region from the system address space to an eBIOS portion of the BIOS image on the NVM device; and
sending second instructions from the processor to the NVM BIOS controller to load the eBIOS portion of the BIOS image from the NVM device into the eBIOS region of the system address space.

18. The method of claim 17 , wherein mapping the eBIOS region from the system address space to the eBIOS portion of the BIOS image further comprises mapping the eBIOS region to a first eBIOS portion of a first BIOS image and mapping the eBIOS region to a second eBIOS portion of a second BIOS image.

19. The method of claim 17 , further comprising:
configuring, by the processor, a state of the enable/disable switch; and
programming, by the processor to the IOH and to the NVM BIOS controller, the eBIOS address range if the state is set to “enable”.

Assignees

• Intel Corp

Inventors

• Radhakrishnan Sivakumar
• Natu Mahesh S
• Zhu Zhenyu
• Trivedi Malay
• Albion Randall L
• Ruffin Chris

Classifications

• G06F2212/206

  Memory mapped I/O · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title