Virtually addressable hardware global kernel segment table

Patent metadata

Field	Value
Publication number	US-10324838-B2
Application number	US-201715730989-A
Country	US
Kind code	B2
Filing date	Oct 12, 2017
Priority date	Oct 12, 2017
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.

First claim

What is claimed is:

1. A method of managing an address translation in a virtually segmented memory system, the method comprising:
creating a global kernel segment table (STAB) that includes an effective address segment number (ESID) to a system wide unique virtual segment identifier (VSID) segment table entry (STE) used by a reload handler;
initiating a switch to the global kernel STAB in response to a page fault or interrupt;
initiating a switch to an original STAB to resume an address translation; and
resolving the page fault or the interrupt by an operating system executing on the processor.

2. The method of claim 1 , further comprising attempting the address translation using the original STAB prior to switching to the global kernel STAB.

3. The method of claim 1 , wherein the global kernel STAB includes a plurality of pinned page table entries (PTEs).

4. The method of claim 3 , wherein the plurality of PTEs cannot be removed and remain accessible.

5. The method of claim 1 , wherein the switching in response to a page fault or interrupt further includes switching in response to the interrupt being generated for a STAB page table entry (PTE) miss.

6. The method of claim 5 , further comprising determining whether the STAB PTE miss occurred while running the PTE reload interrupt handler, itself.

7. The method of claim 1 , wherein the operating system resumes the address translation after the switch to the original STAB.

8. The method of claim 1 , wherein the switching to the global kernel STAB is initiated by the reload handler.

9. The method of claim 8 , wherein reload handler is a page table entry (PTE) reload handler.

10. The method of claim 1 , further comprising adding a small amount of code to the start of the reload handler before virtual page translation has been enabled for the rest of the reload handler.

11. The method of claim 1 , further comprising configuring the global kernel STAB to include only code paths that cannot handle a STAB PTE miss.

12. The method of claim 1 , further comprising configuring the global kernel STAB to include only ESID to VSID mappings for global kernel addresses used to load paging table entries of STAB s.

13. The method of claim 1 , further comprising accessing the global kernel STAB in response to data missing for the original STAB.

14. An apparatus comprising:
a processor; and
a memory storing program code executable by the processor to perform an operation comprising:
create a global kernel segment table (STAB) that includes an effective address segment number (ESID) to a system wide unique virtual segment identifier (VSID) segment table entry (STE) used by a reload handler;
initiate a switch to the global kernel STAB in response to a page fault or interrupt;
initiate a switch to an original STAB to resume an address translation; and
resolve the page fault or the interrupt by an operating system executing on the processor.

15. The apparatus of claim 14 , further comprising attempting the address translation using the original STAB prior to switching to the global kernel STAB.

16. The apparatus of claim 14 , wherein the global kernel STAB includes a plurality of pinned page table entries (PTEs).

17. The apparatus of claim 14 , wherein the switch in response to a page fault or interrupt further includes switching in response to the interrupt being generated for a STAB page table entry (PTE) miss.

18. A computer program product comprising:
a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
creating a global kernel segment table (STAB) that includes an effective address segment number (ESID) to a system wide unique virtual segment identifier (VSID) segment table entry (STE) used by a reload handler;
initiating a switch to the global kernel STAB in response to a page fault or interrupt;
initiating a switch to an original STAB to resume an address translation; and
resolving the page fault or the interrupt by an operating system executing on the processor.

19. The computer program product of claim 18 , further comprising attempting the address translation using the original STAB prior to switching to the global kernel STAB.

20. The computer program product of claim 18 , wherein the global kernel STAB includes a plurality of pinned page table entries (PTEs).

Assignees

• IBM

Inventors

• Flores Arnold
• Mealey Bruce G
• Rogers Mark D

Classifications

• G06F2212/683

  Invalidation · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/1054 Primary

  the data cache being concurrently physically addressed · CPC title